Silicon spin qubits from laboratory to industry

Abstract

Quantum computation is one of the most challenging quantum technologies that promise to revolutionize data computation in the long-term by outperforming the classical supercomputers in specific applications. Errors will hamper this quantum revolution if not sufficiently limited and corrected by quantum error correction codes thus avoiding quantum algorithm failures. In particular millions of highly-coherent qubits arranged in a two-dimensional array are required to implement the surface code, one of the most promising codes for quantum error correction. One of the most attractive technologies to fabricate such large number of almost identical high-quality devices is the well known metal-oxide-semiconductor (MOS) technology. Silicon quantum processor manufacturing can leverage the technological developments achieved in the last 50 years in the semiconductor industry. Here, we review modeling, fabrication aspects and experimental figures of merit of qubits defined in the spin degree of freedom of charge carriers confined in quantum dots and donors in silicon devices along with classical electronics innovations for qubit control and readout. Furthermore, we discuss potential applications of the technology and finally we review the role of start-ups and companies in the silicon-based quantum computing era.

Thin and locally dislocation-free SiGe virtual substrate fabrication by lateral selective growth

“…Si pillar seems to be pinned with the BOX and the SiO 2 cap during the cooling because of lower thermal energy, resulting in tensile strain formation. In the μ-Raman spectrum measured at ∼1 μm away from the Si pillar toward [1][2][3][4][5][6][7][8][9][10] direction [Shown as a red rectangle in Fig. 1(a)], the Si-Si peak at 516.0 cm −1 assigned to the Si pillar has disappeared.…”

“…The tensile strain is caused by the difference in thermal expansion between Si and SiGe and by the partial compressive strain of SiGe in lateral direction. The degree of the strain is slightly higher at the corner of the SiGe because the diagonal area is pulled by both [1][2][3][4][5][6][7][8][9][10] and [−1-10] directions. The Ge incorporation is increased by the tensile strain.…”

“…Virtual substrates (VS) of group IV materials such as SiGe and Ge are essential for fabricating high-performance and emerging devices. [1][2][3][4][5] However, because the SiGe VS is fabricated by heteroepitaxy on a Si substrate, strain is formed at the interface. Therefore, surface roughening and crystalline defect formation, which are caused by the strain fluctuation, cannot be avoided.…”