Silicon Photonics for Exascale Systems

Rumley, Sébastien; Nikolova, Dessislava; Hendry, Robert; Li, Qi; Calhoun, David M.; Bergman, Keren

doi:10.1109/jlt.2014.2363947

Cited by 109 publications

(46 citation statements)

References 86 publications

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“…At the turn of the millennium, however, the scaling limitation of a single processor [9] became apparent. This triggered renewed interest in interconnection structures, in particular in those supported by high radix switches [20].…”

Section: Related Workmentioning

confidence: 99%

“…Networks are thus growing contributors to overall energy consumption -and subsequently dissipation, which is also a serious concern. On the other hand, increased expectations in terms of aggregated computing power, coupled with the progressive saturation of both CPU and chip computing power, leads to a general inflation of the interconnect size [9]. As underlined in several studies (e.g.…”

Section: Introductionmentioning

confidence: 97%

“…As pointed out in several studies [3,13], switches with port counts in this range are currently available, with line rates of several tens of Gb/s. However, Exascale HPC systems will require much larger line rates, in the range of the Tb/s [9]. In this context, the requirement of 100 port switches will become a challenge.…”

mentioning

confidence: 99%

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Design Methodology for Optimizing Optical Interconnection Networks in High Performance Systems

Rumley

Glick

Hammond

et al. 2015

Lecture Notes in Computer Science

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Abstract. Modern high performance computers connect hundreds of thousands of endpoints and employ thousands of switches. This allows for a great deal of freedom in the design of the network topology. At the same time, due to the sheer numbers and complexity involved, it becomes more challenging to easily distinguish between promising and improper designs. With ever increasing line rates and advances in optical interconnects, there is a need for renewed design methodologies that comprehensively capture the requirements and expose trade-offs expeditiously in this complex design space. We introduce a systematic approach, based on Generalized Moore Graphs, allowing one to quickly gauge the ideal level of connectivity required for a given number of end-points and traffic hypothesis, and to collect insight on the role of the switch radix in the topology cost. Based on this approach, we present a methodology for the identification of Pareto-optimal topologies. We apply our method to a practical case with 25,000 nodes and present the results.

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Section: Related Workmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 97%

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Design Methodology for Optimizing Optical Interconnection Networks in High Performance Systems

Rumley

Glick

Hammond

et al. 2015

Lecture Notes in Computer Science

Self Cite

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“…Photonic integrated circuits are now playing a role in advanced technologies with applications ranging from atmospheric spectroscopy [2] and medical diagnostics [3][4][5][6][7] to telecommunications [8,9], data centers, [10,11] and supercomputers [12,13]. Each of these integrated photonic application spaces opens new possibilites for science and technology.…”

Section: Introductionmentioning

confidence: 99%

Room-temperature-deposited dielectrics and superconductors for integrated photonics

Shainline¹,

Buckley²,

Nader³

et al. 2017

Opt. Express

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We present an approach to fabrication and packaging of integrated photonic devices that utilizes waveguide and detector layers deposited at near-ambient temperature. All lithography is performed with a 365 nm i-line stepper, facilitating low cost and high scalability. We have shown low-loss SiN waveguides, high-Q ring resonators, critically coupled ring resonators, 50/50 beam splitters, Mach-Zehnder interferometers (MZIs) and a process-agnostic fiber packaging scheme. We have further explored the utility of this process for applications in nonlinear optics and quantum photonics. We demonstrate spectral tailoring and octave-spanning supercontinuum generation as well as the integration of superconducting nanowire single photon detectors with MZIs and channel-dropping filters. The packaging approach is suitable for operation up to 160 • C as well as below 1 K. The process is well suited for augmentation of existing foundry capabilities or as a stand-alone process.

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“…For example, high-performance PICs in both silicon 1 and InP 2,3 platforms are playing an increasingly important role in data applications with the potential to enable exascale computing 4 and on-chip core-to-core optical communication. 5 Similarly, wide-band gap semiconductors, such as diamond [6][7][8][9][10][11][12][13] and SiC, 14 have emerged as promising materials for a plethora of new PIC applications.…”

mentioning

confidence: 99%

Single-mode optical waveguides on native high-refractive-index substrates

Grote¹,

Bassett²

2016

APL Photonics

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High-refractive-index semiconductor optical waveguides form the basis for modern photonic integrated circuits (PICs). However, conventional methods for achieving optical confinement require a thick lower-refractive-index support layer that impedes large-scale co-integration with electronics and limits the materials on which PICs can be fabricated. To address this challenge, we present a general architecture for single-mode waveguides that confine light in a high-refractive-index material on a native substrate. The waveguide consists of a high-aspect-ratio fin of the guiding material surrounded by lower-refractive-index dielectrics and is compatible with standard top-down fabrication techniques. This letter describes a physically intuitive, semi-analytical, effective index model for designing fin waveguides, which is confirmed with fully vectorial numerical simulations. Design examples are presented for diamond and silicon at visible and telecommunications wavelengths, respectively, along with calculations of propagation loss due to bending, scattering, and substrate leakage. Potential methods of fabrication are also discussed. The proposed waveguide geometry allows PICs to be fabricated alongside silicon CMOS electronics on the same wafer, removes the need for heteroepitaxy in III-V PICs, and will enable wafer-scale photonic integration on emerging material platforms such as diamond and SiC.

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Silicon Photonics for Exascale Systems

Cited by 109 publications

References 86 publications

Design Methodology for Optimizing Optical Interconnection Networks in High Performance Systems

Design Methodology for Optimizing Optical Interconnection Networks in High Performance Systems

Room-temperature-deposited dielectrics and superconductors for integrated photonics

Single-mode optical waveguides on native high-refractive-index substrates

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