Silicon-photonic network architectures for scalable, power-efficient multi-chip systems

Koka, Pranay; McCracken, Michael O.; Schwetman, Herb; Zheng, Xuezhe; Ho, Ron; Krishnamoorthy, Ashok V.

doi:10.1145/1815961.1815977

Cited by 56 publications

(27 citation statements)

References 31 publications

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“…Sun Labs/Oracle researchers [7] recently investigated using silicon photonics for the interconnection network of a multi-chip system or "Macrochip". They analyzed three different photonic networks in the multi-die system that used mirrors to couple light between dies, and concluded that a statically routed point-to-point network outperformed the other networks analyzed.…”

Section: Related Workmentioning

confidence: 99%

“…They analyzed three different photonic networks in the multi-die system that used mirrors to couple light between dies, and concluded that a statically routed point-to-point network outperformed the other networks analyzed. The point-to-point networks analyzed in [7] were limited to 2-bit site-to-site connections, which the authors admit "is a potential performance limiter". The inter-layer coupler assumed in [7] differs from our photonic vias in that the inter-layer coupler connects signals between two dies, where our photonic via couples between layers of the same die.…”

Section: Related Workmentioning

confidence: 99%

“…The point-to-point networks analyzed in [7] were limited to 2-bit site-to-site connections, which the authors admit "is a potential performance limiter". The inter-layer coupler assumed in [7] differs from our photonic vias in that the inter-layer coupler connects signals between two dies, where our photonic via couples between layers of the same die.…”

Section: Related Workmentioning

confidence: 99%

See 2 more Smart Citations

DCAF - A Directly Connected Arbitration-Free Photonic Crossbar for Energy-Efficient High Performance Computing

Nitta

Farrens

Akella

2012

2012 IEEE 26th International Parallel and Distributed Processing Symposium

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Abstract-DCAF is a directly connected arbitration free photonic crossbar that is realized by taking advantage of multiple photonic layers connected with photonic vias. In order to evaluate DCAF we developed a detailed implementation model for the network and analyzed the power and performance on a variety of benchmarks, including SPLASH-2 and synthetic traces. Our results demonstrate that the overhead required by arbitration is non-trivial, especially at high loads. Eliminating the need for arbitration, sizing the buffers carefully and retransmitting lost packets when there is contention results in a 44% reduction in average packet latency without additional power overhead. We also use an analytical model for ScaLAPACK QR decomposition and find that a 64 processor DCAF could outperform a 1024 node cluster connected with 40Gbps links on matrices up to ∼500MB in size.

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Section: Related Workmentioning

confidence: 99%

Section: Related Workmentioning

confidence: 99%

Section: Related Workmentioning

confidence: 99%

See 1 more Smart Citation

DCAF - A Directly Connected Arbitration-Free Photonic Crossbar for Energy-Efficient High Performance Computing

Nitta

Farrens

Akella

2012

2012 IEEE 26th International Parallel and Distributed Processing Symposium

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“…These proposals explore different single-stage topologies from buses [1]- [5] to crossbars [1], [6]- [9] and different multistage topologies from quasi-butterflies [10]- [17] to tori [18]- [20]. Most proposals use different routing algorithms, flow control mechanisms, optical wavelength organizations, and physical layouts.…”

mentioning

confidence: 99%

“…1, the silicon ring resonator is used in transmitters, passive filters, and receivers. Although other photonic structures (e.g., Mach-Zehnder interferometers) are possible, ring modulators are extremely compact (3)(4)(5)(6)(7)(8)(9)(10) radius) resulting in reduced area and power consumption. Although not shown in Fig.…”

mentioning

confidence: 99%

Designing Chip-Level Nanophotonic Interconnection Networks

Batten

Joshi

Stojanović

et al. 2012

IEEE J. Emerg. Sel. Topics Circuits Syst.

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Abstract-Technology scaling will soon enable high-performance processors with hundreds of cores integrated onto a single die, but the success of such systems could be limited by the corresponding chip-level interconnection networks. There have been many recent proposals for nanophotonic interconnection networks that attempt to provide improved performance and energy-efficiency compared to electrical networks. This paper discusses the approach we have used when designing such networks, and provides a foundation for designing new networks. We begin by briefly reviewing the basic silicon-photonic device technology before outlining design issues and surveying previous nanophotonic network proposals at the architectural level, the microarchitectural level, and the physical level. In designing our own networks, we use an iterative process that moves between these three levels of design to meet application requirements given our technology constraints. We use our ongoing work on leveraging nanophotonics in an on-chip title-to-tile network, processor-to-main-memory network, and dynamic random-access memory (DRAM) channel to illustrate this design process.

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References

2016

Modeling and Optimization of Parallel and Distributed Embedded Systems

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Silicon-photonic network architectures for scalable, power-efficient multi-chip systems

Cited by 56 publications

References 31 publications

DCAF - A Directly Connected Arbitration-Free Photonic Crossbar for Energy-Efficient High Performance Computing

DCAF - A Directly Connected Arbitration-Free Photonic Crossbar for Energy-Efficient High Performance Computing

Designing Chip-Level Nanophotonic Interconnection Networks

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