2019
DOI: 10.1109/jstqe.2019.2917501
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Silicon Photonic Circuit Design Using Rapid Prototyping Foundry Process Design Kits

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Cited by 73 publications
(34 citation statements)
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“…Different types of manufacturing process are offered to meet the needs of fabless designers, based on different material platforms, technology nodes, volumes of chips, turnaround time, and cost. For proof-of-concepts, rapid prototyping services (ex: AMO, Applied Nano Tool, Cornerstone, CNM/VLC, LIGENTEC) offer fast turnarounds but low functionalities and low volumes of chips, in part because their fabrication process often relies on e-beam lithography [71] instead of photolithography (exceptions include Cornerstone that uses 248 nm photolithography). Silicon photonic manufacturing is advancing toward both standardization and diversification in terms of materials, layer thickness, and process.…”
Section: Ecosystem and Trendsmentioning
confidence: 99%
“…Different types of manufacturing process are offered to meet the needs of fabless designers, based on different material platforms, technology nodes, volumes of chips, turnaround time, and cost. For proof-of-concepts, rapid prototyping services (ex: AMO, Applied Nano Tool, Cornerstone, CNM/VLC, LIGENTEC) offer fast turnarounds but low functionalities and low volumes of chips, in part because their fabrication process often relies on e-beam lithography [71] instead of photolithography (exceptions include Cornerstone that uses 248 nm photolithography). Silicon photonic manufacturing is advancing toward both standardization and diversification in terms of materials, layer thickness, and process.…”
Section: Ecosystem and Trendsmentioning
confidence: 99%
“…Device fabrication and testing was carried out through the Silicon Electronic-Photonic Integrated Circuits program [62]. Structures were fabricated using standard 220 nm SOI via 100 keV electron beam lithography and reactive ion etching at the University of Washington, while automated grating coupled device measurements were performed at The University of British Columbia.…”
Section: Fabricationmentioning
confidence: 99%
“…The devices were fabricated on SOI wafers by electronbeam lithography at Applied NanoTools [21]. The BOX layer was 2.0 microns and the silicon device layer was 220 nm.…”
Section: B Device Fabrication and Testmentioning
confidence: 99%