Silicon-on-insulator for high-temperature applications

Vanhoenacker‐Janvier, Danielle; Kaamouchi, M. El; Moussa, M. Si

doi:10.1049/iet-cds:20070117

Cited by 15 publications

(7 citation statements)

References 7 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…From (6) and 7, C gb , C gd , and C gs show no significant differences between FB and BC FETs with the same gate periphery since they are dominantly determined by W. The main differences between these two devices are C db and C sb , which are primarily contributed from V DB and V SB , as depicted in (8) and (9). For the BC FET, the body can be directly controlled by the bias potential, such that V DB and V SB would increase as a negative supply voltage is applied to the body, which leads to the decrease of C db and C sb , reducing the total off-capacitance C OFF in (11).…”

Section: Isolationmentioning

confidence: 96%

See 1 more Smart Citation

Effects and contrasts of silicon‐on‐insulator floating‐body and body‐contacted field‐effect transistors to the design of high‐performance antenna switches

Zhang

et al. 2016

IET Microwaves, Antennas & Propagation

View full text Add to dashboard Cite

A theoretical analysis and contrast of silicon‐on‐insulator (SOI) floating‐body (FB) and body‐contacted (BC) metal–oxide–semiconductor field‐effect transistors (FETs) including insertion loss (IL), isolation, power handling capability as well as harmonics for radio frequency switches applications, are firstly developed in detail. From the presented investigation, lower IL and smaller chip size can be obtained using FB FETs, while the BC devices are beneficial to isolation and harmonics improvement. As an experimental vehicle for the presented analysis, the high‐power single‐pole eight‐throw (SP8T) antenna switches for multi‐mode multi‐band applications, are fabricated in a partially depleted 0.18 μm SOI process based on FB and BC FETs, respectively. At 1.9 GHz, the tested IL, TR × 1 to TR × 3 isolation, and P−0.1 dB of the FB and BC SP8T switches are approximately 0.53/0.65 dB, 27.6/29.3 dB and 38.0/38.4 dBm. For the two cases, the second and third harmonics are −70.6/−75.5 and −60.4/−79.9 dBc, respectively, with a +33 dBm input power at 1.9 GHz. The experimental results strongly support the analysis that the FB FET is a preferred device in low loss or low throw‐count switching design while the BC FET is a better selection in the applications that demand high power and low harmonic.

show abstract

Section: Isolationmentioning

confidence: 96%

“…In the partially-depleted (PD) SOI technology, the doping does not extend all the way to the buried oxide (BOX) layer [7,8]. This means there is a neutral body region below the channel.…”

Section: Introductionmentioning

confidence: 99%

Effects and contrasts of silicon‐on‐insulator floating‐body and body‐contacted field‐effect transistors to the design of high‐performance antenna switches

Zhang

et al. 2016

IET Microwaves, Antennas & Propagation

View full text Add to dashboard Cite

show abstract

“…For partially depleted (PD) SOI process technology, not all of the buried oxide (BOX) layer is doped [ 7 , 8 ]. Therefore, a natural body region is created below the channel.…”

Section: Introductionmentioning

confidence: 99%

A 0.617–2.7 GHz Highly Linear High-Power Dual Port 15 Throws Antenna Switch Module (DP15T-ASM) with Branched-Antenna Technique and Termination Mode

Rad

Choi

Kim

et al. 2022

Sensors

View full text Add to dashboard Cite

This paper presents a Dual-Port-15-Throw (DP15T) antenna switch module (ASM) Radio Frequency (RF) switch implemented by a branched antenna technique which has a high linearity for wireless communications and various frequency bands, including a low- frequency band of 617–960 MHz, a mid-frequency band of 1.4–2.2 GHz, and a high-frequency band of 2.3–2.7 GHz. To obtain an acceptable Insertion Loss (IL) and provide a consistent input for each throw, a branched antenna technique is proposed that distributes a unified magnetic field at the inputs of the throws. The other role of the proposed antenna is to increase the inductance effects for the closer ports to the antenna pad in order to decrease IL at higher frequencies. The module is enhanced by two termination modes for each antenna path to terminate the antenna when the switch is not operating. The module is fabricated in the silicon-on-insulator CMOS process. The measurement results show a maximum IMD2 and IMD3 of −100 dBm, while for the second and third harmonics the maximum value is −89 dBc. The module operates with a maximum power handling of 35 dBm. Experimental results show a maximum IL of 0.34 and 0.92 dB and a minimum isolation of 49 dB and 35.5 dB at 0.617 GHz and 2.7 GHz frequencies, respectively. The module is implemented in a compact way to occupy an area of 0.74 mm2. The termination modes show a second harmonic of 75 dBc, which is desirable.

show abstract

“…This process is based on 200 mm silicon-on-insulator (SOI) wafers. Since common bulk technology comes to its limit at temperatures above 175 C due to increasing pn-leakage currents, the SOI technology is a good concept if temperatures of 250 C or more should be targeted [3,4]. As is necessary for each process, a process which is designed to be used at these high temperatures must be characterized and qualified for the maximum operation temperature.…”

Section: Introductionmentioning

confidence: 99%

Reliability Investigations up to 350°C of Gate Oxide Capacitors Realized in a Silicon-on-Insulator CMOS Technology

Grella¹,

Dreiner²,

Vogt³

et al. 2013

Journal of Microelectronics and Electronic Packaging

View full text Add to dashboard Cite

AbstractÀIt is difficult to use standard bulk-CMOS-technology at temperatures higher than 1758C due to high pn-leakage currents. Silicon-on-insulator-technologies (SOI), on the other hand, are usable up to 2508C and even higher, because leakage currents can be reduced by two to three orders of magnitude. Nevertheless, performance and reliability of SOI devices are strongly affected at these high temperatures. One of the main critical factors is the gate oxide quality and its reliability. In this paper, we present a study of gate oxide capacitor time-dependent dielectric breakdown (TDDB) measurements at temperatures up to 3508C. The experiments were carried out on gate oxide capacitor structures realized in the Fraunhofer 1.0 mm SOI-CMOS process. The gate oxide thickness is 40 nm. Using the data of the TDDB measurements, the behavior of field and temperature acceleration parameters at temperatures up to 3508C was evaluated. For a more detailed investigation, the evolution of the current in time was also studied. An analysis of the oxide breakdown conditions, in particular the field and temperature dependence of the charge to breakdown and the current just before breakdown, completes the study. The presented data provide important information about accelerated oxide reliability testing beyond 2508C, and make it possible to quickly evaluate the reliability of high temperature CMOS technologies at operation temperature.

show abstract

Silicon-on-insulator for high-temperature applications

Cited by 15 publications

References 7 publications

Effects and contrasts of silicon‐on‐insulator floating‐body and body‐contacted field‐effect transistors to the design of high‐performance antenna switches

Effects and contrasts of silicon‐on‐insulator floating‐body and body‐contacted field‐effect transistors to the design of high‐performance antenna switches

A 0.617–2.7 GHz Highly Linear High-Power Dual Port 15 Throws Antenna Switch Module (DP15T-ASM) with Branched-Antenna Technique and Termination Mode

Reliability Investigations up to 350°C of Gate Oxide Capacitors Realized in a Silicon-on-Insulator CMOS Technology

Contact Info

Product

Resources

About