Silicon-nitride as a tunnel dielectric for improved SONOS-type flash memory

She, Min; Takeuchi, Hideki; King, Tsu‐Jae

doi:10.1109/led.2003.812547

Cited by 55 publications

(22 citation statements)

References 7 publications

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“…This endurance degradation is attributed to the interface-trap generation and the electron trapping in the tunneling oxide [15,16]. In order to verify the endurance degradation, a charge pumping method was employed [17,18].…”

Section: Resultsmentioning

confidence: 99%

Investigation of Endurance Degradation in a CTF NOR Array Using Charge Pumping Methods

Kim²

2016

Transactions on Electrical and Electronic Materials

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The NOR-type SONOS memory devices used in this study were fabricated using a standard 0.35 μm complementary-metaloxide-semiconductor (CMOS) technology. In these devices, the We investigate the effect of interface states on the endurance of a charge trap flash (CTF) NOR array using charge pumping methods. The endurance test was completed from one cell selected randomly from 128 bit cells, where the memory window value after 10 2 program/erase (P/E) cycles decreased slightly from 2.2 V to 1.7 V. However, the memory window closure abruptly accelerated after 10 3 P/E cycles or more (i.e. 0.97 V or 0.7 V) due to a degraded programming speed. On the other hand, the interface trap density (Nit) gradually increased from 3.13×10 11 cm -2 for the initial state to 4×10 12 cm -2 for 10 2 P/E cycles. Over 10 3 P/E cycles, the Nit increased dramatically from 5.51×10 12 cm -2 for 10 3 P/E cycles to 5.79×10 12 cm -2 for 10 4 P/E cycles due to tunnel oxide damages. These results show good correlation between the interface traps and endurance degradation of CTF devices in actual flash cell arrays. Ho-Myoung An

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Section: Resultsmentioning

confidence: 99%

Investigation of Endurance Degradation in a CTF NOR Array Using Charge Pumping Methods

Kim²

2016

Transactions on Electrical and Electronic Materials

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“…The slightly larger V th shift upward for Si-QD NVMs are due to the electron trapping in the deep charge-trapping level of Si-QDs or tunneling oxide. 3,5,26 The incomplete removal of the trapped electrons during the erasure operation could also be found from the erase speed characteristic in Fig. 1(c) and leads to the upward shift of V th after increasing P/E cycles.…”

mentioning

confidence: 83%

“…Although the pursuit of thin tunneling oxide enhance the tunneling probability of electrons, 4 it inevitably degrades the reliability of NVMs. 5,6 Therefore, the bandgap engineered tunneling dielectric such as thin Si 3 N 4 (<2 nm) or small Si-QD (1.1 nm) in ultra-thin SiO 2 were proposed to improve the reliability. 7,8 On the other hand, metal gate significantly improves the erase characteristic by additional work-function control 9,10 and eliminates the depletion and dopant diffusion of polycrystalline silicon (poly-Si).…”

mentioning

confidence: 99%

“…The NVMs with Si-QDs exhibit more electron charging nodes between the interface of silicon nitride and Si-QDs or the trapping site in Si-QDs. 2,5 On the other hand, direct tunneling and F-N tunneling mechanisms occur simultaneously when the thickness of tunneling oxide shrinkages to <5 nm. 4 On the part of erase operation, the unwanted electron tunneling current through a blocking oxide is greatly suppressed through higher work function of Al-Si-Cu alloy than n þ poly-Si gate.…”

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confidence: 99%

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Fast programming metal-gate Si quantum dot nonvolatile memory using green nanosecond laser spike annealing

Lien

Shieh

Huang

et al. 2012

Applied Physics Letters

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The ultrafast metal-gate silicon quantum-dot (Si-QD) nonvolatile memory (NVM) with program/ erase speed of 1 ls under low operating voltages of 6 7 V is achieved by thin tunneling oxide, in situ Si-QD-embedded dielectrics, and metal gate. Selective source/drain activation by green nanosecond laser spike annealing, due to metal-gate as light-blocking layer, responds to low thermal damage on gate structures and, therefore, suppresses re-crystallization/deformation/ diffusion of embedded Si-QDs. Accordingly, it greatly sustains efficient charge trapping/de-trapping in numerous deep charge-trapping sites in discrete Si-QDs. Such a gate nanostructure also ensures excellent endurance and retention in the microsecond-operation Si-QD NVM. V

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“…Furthermore, the FGto-FG coupling effect will limit the space between the cells, which is especially serious for NAND flash memory. Recently, SONOS (polysilicon-oxide-nitride-oxide-silicon) memory devices are attracting great interest as a possible replacement for the traditional floating-gate flash EEPROM device, due to the low voltage operation [4], simple process integration [5], elimination of drain-induced turn-on [6] and improved cycling endurance [7]. In addition, a SONOS memory device with a split gate can be fast programmed with low power consumption [8][9][10].…”

Section: Introductionmentioning

confidence: 99%

Optimized ONO thickness for multi-level and 2-bit/cell operation for wrapped-select-gate (WSG) SONOS memory

Chao

Peng

et al. 2007

Semicond. Sci. Technol.

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In this paper, highly reliable wrapped-select-gate (WSG) silicon-oxide-nitride-oxide-silicon (SONOS) memory cells with multi-level and 2-bit/cell operation have been successfully demonstrated. The source-side injection mechanism for WSG-SONOS memory with different ONO thickness was thoroughly investigated. The different programming efficiencies of the WSG-SONOS memory under different ONO thicknesses are explained by the lateral electrical field extracted from the simulation results. Furthermore, multi-level storage is easily obtained, and good V TH distribution presented, for the WSG-SONOS memory with optimized ONO thickness. High program/erase speed (10 µs/5 ms) and low programming current (3.5 µA) are used to achieve the multi-level operation with tolerable gate and drain disturbance, negligible second-bit effect, excellent data retention and good endurance performance.

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Silicon-nitride as a tunnel dielectric for improved SONOS-type flash memory

Cited by 55 publications

References 7 publications

Investigation of Endurance Degradation in a CTF NOR Array Using Charge Pumping Methods

Investigation of Endurance Degradation in a CTF NOR Array Using Charge Pumping Methods

Fast programming metal-gate Si quantum dot nonvolatile memory using green nanosecond laser spike annealing

Optimized ONO thickness for multi-level and 2-bit/cell operation for wrapped-select-gate (WSG) SONOS memory

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