Silicon Nanowire Esaki Diodes

Abstract

We report on the fabrication and characterization of silicon nanowire tunnel diodes. The silicon nanowires were grown on p-type Si substrates using Au-catalyzed vapor-liquid-solid growth and in situ n-type doping. Electrical measurements reveal Esaki diode characteristics with peak current densities of 3.6 kA/cm(2), peak-to-valley current ratios of up to 4.3, and reverse current densities of up to 300 kA/cm(2) at 0.5 V reverse bias. Strain-dependent current-voltage (I-V) measurements exhibit a decrease of the peak tunnel current with uniaxial tensile stress and an increase of 48% for 1.3 GPa compressive stress along the <111> growth direction, revealing the strain dependence of the Si band structure and thus the tunnel barrier. The contributions of phonons to the indirect tunneling process were probed by conductance measurements at 4.2 K. These measurements show phonon peaks at energies corresponding to the transverse acoustical and transverse optical phonons. In addition, the low-temperature conductance measurements were extended to higher biases to identify potential impurity states in the band gap. The results demonstrate that the most likely impurity, namely, Au from the catalyst particle, is not detectable, a finding that is also supported by the excellent device properties of the Esaki diodes reported here.

First-principles electron transport with phonon coupling: Large scale at low cost

“…This is traced back to an increased window for inelastic transmission across the device that scales with the bias window. Again, this trend fits with the experiments performed by Schmid et al [47] Carrier mobilities. Carrier mobilities limited by EPC is an important performance indicator of materials.…”

“…In Fig. 2 we consider transport in a short (6.5 nm) and a long (19.6 nm) silicon p-n junction [7,47,48] with transport in the [100] crystal direction.…”

Observation of negative differential conductance in nanoscale p-n junctions

“…The tunneling in forward-bias mode can be seen as negative differential conductance (NDC), i.e, a negative slope in current-voltage (I-V) curve. So far, tunneling in nanometer-scale p-n junctions has been reported in vertical nanowires in forward-bias mode [6,7] and in lateral gated p-n junctions in reverse-bias mode [8]. In this work, we study nanoscale lateral p-n junctions in forward-bias mode and report the experimental observation of NDC at low temperatures.…”

Observation of Tunneling Effects in Lateral Nanowire pn Junctions

“…So far, research about tunneling in nanometer-scale pn junctions has been reported mainly for vertical structures [6][7][8]. Tunneling in lateral pn junctions has been reported by Aydin et al [9], but not in nanowire structures.…”