1988
DOI: 10.1016/0011-2275(88)90038-0
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Silicon junction field effect transistors at 4.2 K

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Cited by 8 publications
(1 citation statement)
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“…The optimization of noise in the typical silicon JFET requires elevation of the temperature (above ∼120 K) with some thermal standoff or heater, which can increase stray capacitance at the JFET gate. Custom JFETs which function down to 4 K [28] are not available with the low (< 1 pF) capacitance required for ultra-low noise detector front end electronics. While the transconductances of both JFET and MOSFET improve continually as the temperature is lowered [29], the relatively high minimum operating temperature of JFETs directly support the use of MOSFETs below LN 2 temperatures where HPGe leakage currents may also improve.…”
Section: Cmos Front End Electronicsmentioning
confidence: 99%
“…The optimization of noise in the typical silicon JFET requires elevation of the temperature (above ∼120 K) with some thermal standoff or heater, which can increase stray capacitance at the JFET gate. Custom JFETs which function down to 4 K [28] are not available with the low (< 1 pF) capacitance required for ultra-low noise detector front end electronics. While the transconductances of both JFET and MOSFET improve continually as the temperature is lowered [29], the relatively high minimum operating temperature of JFETs directly support the use of MOSFETs below LN 2 temperatures where HPGe leakage currents may also improve.…”
Section: Cmos Front End Electronicsmentioning
confidence: 99%