Recent advances in spatial light modulator technology involves the integration of electronic circuitry with either optical modulators or emitters. In particular, much of this work has focused on the marriage of CMOS silicon with III–V emitter/modulating materials. The advantage of this approach is the high speeds attainable with III–V multiple quantum well devices. The disadvantage is the difficulty of integration with silicon circuits of more than a few transistors. Currently, most III–IV smart SLMs are made in small array sizes, i.e., less than 16 × 16. For uses requiring many smart pixels such as image processing, neural networks, and displays, another approach is to fabricate liquid crystals on top of silicon CMOS circuits. These devices include 176 × 176 electrically addressed DRAM SLMs1 and 64 × 64 SRAMs,2 and 32 × 32 optically addressed thresholding arrays.3