Signal Processing with Teams of Embedded Workhorse Processors

Hobson, R. F.; Dyck, Adam; Cheung, K-John; Ressl, B.

doi:10.1155/es/2006/69484

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Managing a Heterogeneous Architecture1

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Cited by 2 publications

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“…The heterogeneous architecture is not as easy to program as the homogeneous architecture that consist of similar processing elements. Homogenous architectures are easy to implement on silicon (picoChip, 2007, Hobson et al, 2006). Heterogeneous architectures provide greater yields in execution speeds because they include dedicated processing elements for specific application tasks, some elements are designed to speed up code.…”

Section: Managing a Heterogeneous Architecturementioning

confidence: 99%

A SystemC Cache Simulator for a Multiprocessor Shared Memory System

Mutanga

2013

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In this research we built a SystemC Level-1 data cache system in a distributed shared memory architectural environment, with each processor having its own local cache. Using a set of Fast-Fourier Transform and Random trace files we evaluated the cache performance, based on the number of cache hits/misses, of the caches using snooping and directory-based cache coherence protocols. A series of experiments were carried out, with the results of the experiments showing that the directory-based MOESI cache coherency protocol has a performance edge over the snooping Valid-Invalid cache coherency protocol.

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Section: Managing a Heterogeneous Architecturementioning

confidence: 99%