Abstract:In this paper, the signal integrity and power integrity of mesh patterns are investigated in the Double Data Rate 4 Small Outline Dual In-line Memory Module (DDR4 SODIMM). The mesh patterns are designed to be a square in the power plane and are repeated periodically with a spacing of 1 mm. The sizes of the mesh patterns are considered in terms of the operating speed of the DDR4 SODIMM and its wavelength. The effect of signal integrity on the address line is analyzed as the mesh size increases. The eye-diagram … Show more
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