Signal-Margin-Screening for Multi-Mb MRAM

Honigschmid, H.; Beer, P.; Bette, Ann-Christin; Dittrich, R.; Gardic, R.; Gogl, D.; Lammers, S.; Schmid, Jérôme; Altimime, L.; Bournat, S.; Müller, Georg

doi:10.1109/isscc.2006.1696079

Cited by 10 publications

(2 citation statements)

References 3 publications

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“…Previous implementations of transistor-option calibration-based CSA (TO-CSA) [22] used an asymmetric number of transistors (or transistor strength/width) along the various paths in a CSA in order to achieve offset suppression. To obtain options of offset suppression, each TO-CSA requires transistors and switches.…”

Section: A Comparisonmentioning

confidence: 99%

An Asymmetric-Voltage-Biased Current-Mode Sensing Scheme for Fast-Read Embedded Flash Macros

Chang

Lin

Liu

et al. 2015

IEEE J. Solid-State Circuits

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Current-mode sense amplifiers (CSA) are commonly used in eNVM, because of their fast read speed at large bitline (BL) loads and small cell read currents. However, conventional CSAs are unable to achieve fast random read access time , due to significant summed input offsets at read-path. This work proposes a calibration-based asymmetric-voltage-biased CSA (AVB-CSA) to suppress and enable high-speed sensing without the need for run-time offset-cancellation operations. This work then fabricated two 90 nm AVB-CSA 1 Mb Flash testchips (with and without BL-length test-modes). The AVB-CSA eFlash macros with 512 rows achieved of 3.9 ns at nominal VDD (1.2 V). The BL-length test-mode experiments confirmed a improvement in using AVB-CSA with a BL-length of 2048-rows operating at V. Index Terms-Current-mode sense amplifier (CSA), Flash.

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Section: A Comparisonmentioning

confidence: 99%

An Asymmetric-Voltage-Biased Current-Mode Sensing Scheme for Fast-Read Embedded Flash Macros

Chang

Lin

Liu

et al. 2015

IEEE J. Solid-State Circuits

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“…The sensing circuit in [11] ideally achieves twice the gain of the sensing circuit in Figure 4 using a highly symmetric cross-coupled current mirror amplifier. However, additional matching requirements due to more matched-pair transistors increase the sense amplifier offset [13]. As comparison, the sensing circuit in [12] adopted the resistance-mean reference scheme with a current conveyor and a differential amplifier.…”

Section: Mram Sensing Circuitsmentioning

confidence: 99%

Sensing margin trend with technology scaling in MRAM

Song

Kim

Kang

et al. 2011

Circuit Theory & Apps

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SUMMARYMagnetoresistive random access memory (MRAM) is a leading candidate for future memory applications because it may provide compelling advantages by combining desirable attributes of SRAM, DRAM, and Flash. Process technology has recently scaled down to the nano-meter regime, which accordingly has resulted in lowering supply voltage, increasing short channel effect, and rapidly increasing process variation. MRAM is also affected by technology scaling, which significantly reduces the sensing margin. In this paper, several circuit design parameters, such as supply voltage, transistor size, and transistor gate voltage in the sensing circuit, are evaluated to discover the root causes of reduced sensing margin with technology scaling. The lowered supply voltage and lowered output resistance of the transistor, which occurs with technology scaling, are verified as the root causes of reduced sensing margin. It is also shown that increased process variation due to technology scaling aggravates the problem. A high supply voltage with power gating combined with optimized transistor size and gate voltage, and a power gating scheme using an IO device with an IO voltage are suggested as effective design solutions for reliably increasing the sensing margin in the presence of process variation.

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