Signal Integrity of Submicron InFO Heterogeneous Integration for High Performance Computing Applications

Wang, Chuei-Tang; Hsieh, Jeng-Shien; Chang, Victor C. Y.; Huang, Shih-Ya; Ko, Tze‐Man; Pu, H. P.; Yu, Douglas

doi:10.1109/ectc.2019.00109

Cited by 21 publications

(2 citation statements)

References 10 publications

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“…Fig. 22 illustrates a conceptual diagram for one of the representative technologies (i.e., INFO process from TSMC) used to integrate multiple chiplets that are connected by a redistribution layer (RDL) with an ultrafine pitch [54]. The INFO package has been demonstrated to integrate antenna elements recently for millimeter-wave applications [55].…”

Section: ) Wafer Level Packagementioning

confidence: 99%

Packaging and Antenna Integration for Silicon-Based Millimeter-Wave Phased Arrays: 5G and Beyond

Liu

Sadhu

2021

IEEE J. Microw.

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Section: ) Wafer Level Packagementioning

confidence: 99%

Packaging and Antenna Integration for Silicon-Based Millimeter-Wave Phased Arrays: 5G and Beyond

Liu

Sadhu

2021

IEEE J. Microw.

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“…Here, the die was manufactured by creating a copper circuit on a silicon substrate and then deicing it to the desired size [10][11][12]. The silicon etching method must be used for all samples to study die thinning formed in this manner.…”

Section: Introductionmentioning

confidence: 99%

Die level thinning after bonding on the substrate in 3D packaging

Wang

Hu²,

Xiao³

et al. 2023

J. Phys.: Conf. Ser.

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This paper aims to realize heterogeneous integrated packaging technology for high integration by applying a thinning process technology for controlling the thickness of chipsets used in packaging, i.e., A technology for processing silicon dies with a thickness of 100 um or less and a technology for handling thinning ultrasmall dies. We combine wet etching with dry etching to fit an effective and practical experimental plan. Anisotropic etching in KOH solutions and ICP etching of silicon die bonding on a glass substrate are investigated. Die with copper wiring is fabricated and pasted on the substrate to achieve selective etching of the whole device. The topography of the die surface and corner is analyzed to prevent the influence on the second layer stacking process.

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