Signal Integrity Design and Analysis of Differential High-Speed Serial Links in Silicon Interposer With Through-Silicon Via

Cho, Kyungjun; Kim, Youngwoo; Lee, Deokjung; Song, Jinwook; Park, Junyong; Lee, Seongsoo; Kim, Subin; Park, Gapyeol; Son, Kyungjune; Kim, Joungho

doi:10.1109/tcpmt.2018.2843442

Cited by 29 publications

(16 citation statements)

References 18 publications

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“…The new interposer channel solution should alleviate the influence of impedance discontinuity and minimize the issue of off-chip power consumption, while not causing a routing issue. Regarding signal integrity, previous research on the HBM interface has been carried out in various ways, which can be divided into several categories [4,[6][7][8][9][10]. Refs.…”

Section: Introductionmentioning

confidence: 99%

“…Moreover, it is not possible to fundamentally improve the cause of channel loss in the case of impedance mismatching, reflection, etc. With DBI coding, a DBI channel is required, so issues with Regarding signal integrity, previous research on the HBM interface has been carried out in various ways, which can be divided into several categories [4,[6][7][8][9][10]. Refs.…”

Section: Introductionmentioning

confidence: 99%

“…Since the channel is relatively wide, the impedance formed is inevitably very small. In [ 4 ], in order to increase the impedance of the interposer channel, the ground slot under the signal channel was presented. Secondly, from the paper [ 5 ], the power consumption of an off-chip interconnection was found to be generally 100 times larger than that on-chip.…”

Section: Introductionmentioning

confidence: 99%

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A Novel Interposer Channel Structure with Vertical Tabbed Vias to Reduce Far-End Crosstalk for Next-Generation High-Bandwidth Memory

et al. 2022

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In this paper, we propose and analyze a novel interposer channel structure with vertical tabbed vias to achieve high-speed signaling and low-power consumption in high-bandwidth memory (HBM). An analytical model of the self- and mutual capacitance of the proposed interposer channel is suggested and verified based on a 3D electromagnetic (EM) simulation. We thoroughly analyzed the electrical characteristics of the novel interposer channel considering various design parameters, such as the height and pitch of the vertical tabbed via and the gap of the vertical channel. Based on the frequency-dependent lumped circuit resistance, inductance, and capacitance, we analyzed the channel characteristics of the proposed interposer channel. In terms of impedance, insertion loss, and far-end crosstalk, we analyzed how much the proposed interposer channel improved the signal integrity characteristics compared to a conventional structure consisting of micro-strip and strip lines together. Compared to the conventional worst case, which is the strip line, the eye-width, the eye-height, and eye-jitter of the proposed interposer channel were improved by 17.6%, 29%, and 9.56%, respectively, at 8 Gbps. The proposed interposer channel can reduce dynamic power consumption by about 28% compared with the conventional interposer channel by minimizing the self-capacitance of the off-chip channel.

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Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

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A Novel Interposer Channel Structure with Vertical Tabbed Vias to Reduce Far-End Crosstalk for Next-Generation High-Bandwidth Memory

et al. 2022

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“…While the impedance variation was reduced, the mode conversion did not significantly improve. Moreover, in silicon interposer, which has been actively studied recently, various design parameters in a meshed ground for impedance matching have been studied, but no new structure has been proposed [16,17]. We introduced an offset mesh structure to alleviate the impedance variation of single-ended lines [18].…”

Section: Introductionmentioning

confidence: 99%

Improving Signal Integrity by Reducing Mode Conversion in Differential Pairs on a Meshed Ground in Flexible Printed Circuit Boards

Kam

2022

J Electromagn Eng Sci

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Asymmetry in a differential pair leads to deterioration of signal integrity. Differential pairs on a meshed ground often encounter asymmetry in return current paths. In this paper, we propose an offset mesh as an improved mesh structure that offsets asymmetry between a solid region and an aperture region. The offset mesh mitigates the asymmetry in the conventional mesh structure without additional design elements. The proposed structure has been verified to be effective in reducing mode conversion, intra-pair and inter-pair skews, and characteristic impedance variation in the time and frequency domains. This enables high-density routing of differential pairs.

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“…In addition, it is challenging to arrange the lines and the meshed ground completely symmetrically in actual production [13]. If the two are even slightly asymmetrical, the characteristic impedance changes [14,15,16], causing mode conversion and differential skew [17,18,19].…”

Section: Introductionmentioning

confidence: 99%

Mitigating differential skew by rotating meshed ground for high-density layout in flexible printed circuits

Wang

Iokibe

Toyota

2020

IEICE Electron. Express

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Asymmetry of differential transmission lines over a meshed ground plane causes differential skew, which leads to signal integrity issues. We measured to evaluate how the angle between the differential transmission lines and meshed ground (the rotation angle) affected differential skew. We also investigated the effect of the lines' position on characteristic impedance and the feasibility of high-density layout of the differential transmission lines, including the bend structure. We found that the differential skew and characteristic impedance are not significantly affected by the position of the differential transmission lines and meshed ground when the rotation angle is set to 30 • , a relatively small value. Measurements showed that our design is effective.

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Signal Integrity Design and Analysis of Differential High-Speed Serial Links in Silicon Interposer With Through-Silicon Via

Cited by 29 publications

References 18 publications

A Novel Interposer Channel Structure with Vertical Tabbed Vias to Reduce Far-End Crosstalk for Next-Generation High-Bandwidth Memory

A Novel Interposer Channel Structure with Vertical Tabbed Vias to Reduce Far-End Crosstalk for Next-Generation High-Bandwidth Memory

Improving Signal Integrity by Reducing Mode Conversion in Differential Pairs on a Meshed Ground in Flexible Printed Circuit Boards

Mitigating differential skew by rotating meshed ground for high-density layout in flexible printed circuits

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