SIGMA-1: A dataflow computer for scientific computations

Yuba, Toshitsugu; Shimada, Takahiro; Hiraki, Kei; Kashiwagi, Hiroshi

doi:10.1016/0010-4655(85)90146-8

Cited by 17 publications

(12 citation statements)

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“…The Manchester team is experimenting with an equalpath-length switch that involves an equal delay for every packet transferred through it. The ETL team is using an hierarchical switch in which local transfers are delayed less than non-local ones [20,24]. The latter should be more efficient, provided that the language level compiler can plant code that exhibits suitable locality.…”

Section: Machine Architecturementioning

confidence: 99%

“…Over the past decade, a widespread consensus has been achieved by the dataflow research community concerning the basic underlying model of computation, the organisation of machines, and appropriate high-level programming languages. The principal sites at which practical dataflow research is being conducted, and from which the following presentation is drawn, are the Massachussetts Institutes for Technology (MIT) in the United States of America [4], the ElectroTechnical Laboratory (ETL) in Japan [20,24], and the University of Manchester in England [12,13]. The following sections express the consensus between these groups by inspecting an example of a practical dataflow computing system, the Manchester Dataflow Machine (MDFM), that has been implemented and evaluated at the author's institution.…”

Section: Introductionmentioning

confidence: 99%

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Performance issues in dataflow machines

Gurd

Bohm

Teo

1987

Future Generation Computer Systems

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Design Issues for Parallel Computers Architectural LevelsThis paper explores issues affecting the performance of a particular style of parallel computer system. In considering such issues, it is important to distinguish between different levels of the system architecture.Broadly speaking, computer systems are designed at three levels. The first, usually thought of as the lowest level, is that of the hardware architec- North-Holland Future Generations Computer Systems 3 (1987) [285][286][287][288][289][290][291][292][293][294][295][296][297] ture and its associated machine-code. This is often referred to as the machine level. The next, intermediate level is that of the so-called high-level programming language, from which machine-code is generated. This is often referred to as the language level. Most often, this is not at a sufficiently high level to express specific applications in a convenient way. Consequently, the highest level, known as the applications level, is constructed for particular application areas on top of the language level. The interface to this level is a kind of 'very-high-level', applications-oriented language.As far as the end-user of a computer system is concerned, performance at the applications level is most important. However, as this varies significantly according to the particular application, and in a somewhat unpredictable fashion, most attempts at evaluating performance are made at the two lower levels. This paper broadly conforms to this pattern, but an attempt is made to relate the performance assessment to a specific set of applications, the so-called scientific problems, which involve a substantial amount of numerical calculation. Parallel WorkloadParallel system performance is predominantly determined by design decisions made at the machine and language levels. The most critical of these decisions concern the nature, identification, distribution and control of the parallel workload.Different basic models of parallel computation can create workloads of a fundamentally different nature. For example, although many parallel programs are written as systems of communicating parallel processes, there is a critical distinction between systems that implement the communication using shared memory and those that use direct message-passing. The workload in the former involves accesses to a hardware third party (the shared memory) that are not necessary in the latter. Also, there is an important difference between such process-based schemes, which split the overall workload into coarse-grain chunks, and systems, such as dataflow, that segregate work into very fine-grain components. The former re- 0376-5075788753.50 © 1988, Elsevier Science Publishers B.V. (North-Holland)

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Section: Machine Architecturementioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Performance issues in dataflow machines

Gurd

Bohm

Teo

1987

Future Generation Computer Systems

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“…Only a few experimental multiprocessors have been built that use the dynamic data-flow model of execution. Most notable are the Manchester dataflow [1], the SIGMA-1 [2], EM-4 [3] and the Monsoon [4]. The work presented in this paper focuses on the design and implementation of a hybrid model that utilizes both controlflow and data-flow.…”

Section: Introductionmentioning

confidence: 99%

Verilog-based simulation of hardware support for data-flow concurrency on multicore systems

Matheou

Evripidou

2013

2013 International Conference on Embedded Computer Systems: Architectures, Modeling, and Simulation (SAMOS)

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Data-Driven Multithreading (DDM) is a threaded data-flow model that schedules threads for execution based on data availability. DDM is utilizing a Thread Scheduling Unit (TSU) for the management of the threads on sequential processors. In this work we present the hardware implementation of the TSU with synthesizable code using the Verilog HDL and its evaluation using the ISim simulator. The evaluation results show that the TSU is able to run at a maximum frequency of 180 MHz and consumes only 5% of the Xilinx Virtex-6 FPGA resources. The initial results obtained in this work will enable us to design an FPGA based DDM multicore chip consisting of several Microblaze cores driven by the TSU. Thus, we will be able to evaluate the performance of the novel threaded data-flow model and have direct comparison with the sequential model on the same hardware.

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“…Supondo que, em adiyao a especificayao de urn no destino, que 0 rotulo tambem especifique uma particular regra de disparo do no, entao, duas fichas participam do mesmo disparo de urn no somente se seus rotulos forem os mesmos. [Shi+83,Yub+87]. 0 principal objetivo era pesquisar e estabelecer uma base tecno16gica para constru'tiio de supercomputadores dataflow altamente paralelos.…”

Section: Reentrancia Em Arquiteturas a Fluxo De Dados Dinamicaunclassified

Estudo da distribuicao de ocorrencias de instrucoes em grafos de dependencia de dados da arquitetura Wolf

Vicentini¹

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2.1 IntrodufiJo 2.2 MIT Tagged Dataflow Architecture-MTTDA 2.3 Monsoon 2.4 SIGMA-I 2. 5 EM-4 Dataflow Multiprocessor 29 2.6 Epsilon-2 Multiprocessor 32 2. 7 p-RISC 34 2.8 TAM (Treaded Abstract Machine) 35 2.9 StarT-NG 35 2.10 Manchester Multi-Ring DaIIIjIow Machine 38 2.11 ConsidertlfOes F",ais sobre Arquiteturas a Fluxo de Dados 39 DESCRIc;:Ao FuNCIONAL DAARQUITETIJRA WOLF E DALINGUAGEM SISAL 41 3.1 IntroduflJo 41 3.2 DescrlfiJo Funcional das Unidodes do Wolf 43

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SIGMA-1: A dataflow computer for scientific computations

Cited by 17 publications

References 1 publication

Performance issues in dataflow machines

Performance issues in dataflow machines

Verilog-based simulation of hardware support for data-flow concurrency on multicore systems

Estudo da distribuicao de ocorrencias de instrucoes em grafos de dependencia de dados da arquitetura Wolf

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