2022
DOI: 10.3390/coatings12030348
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SiGeSn Quantum Dots in HfO2 for Floating Gate Memory Capacitors

Abstract: Group IV quantum dots (QDs) in HfO2 are attractive for non-volatile memories (NVMs) due to complementary metal-oxide semiconductor (CMOS) compatibility. Besides the role of charge storage centers, SiGeSn QDs have the advantage of a low thermal budget for formation, because Sn presence decreases crystallization temperature, while Si ensures higher thermal stability. In this paper, we prepare MOS capacitors based on 3-layer stacks of gate HfO2/floating gate of SiGeSn QDs in HfO2/tunnel HfO2/p-Si obtained by magn… Show more

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Cited by 8 publications
(3 citation statements)
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“…As can be imagined, the SiGeSn crystallization process is hindered if it is embedded in an amorphous oxide matrix, this process requiring the diffusion-segregation for NCs nucleation. Previous studies on a tri-layer memory structure based on a thin floating gate layer of SiGeSn embedded in HfO 2 31 have revealed that the annealing temperature required for the formation of SiGeSn NC is in the range of 500–550 °C. This is also valid for thick amorphous layers of SiGeSnHfO 2 studied in this paper as resulted from HRTEM analysis presented above and the X-ray diffractograms in Fig.…”
Section: Resultsmentioning
confidence: 99%
“…As can be imagined, the SiGeSn crystallization process is hindered if it is embedded in an amorphous oxide matrix, this process requiring the diffusion-segregation for NCs nucleation. Previous studies on a tri-layer memory structure based on a thin floating gate layer of SiGeSn embedded in HfO 2 31 have revealed that the annealing temperature required for the formation of SiGeSn NC is in the range of 500–550 °C. This is also valid for thick amorphous layers of SiGeSnHfO 2 studied in this paper as resulted from HRTEM analysis presented above and the X-ray diffractograms in Fig.…”
Section: Resultsmentioning
confidence: 99%
“…Targeting further improvement of memory properties, besides GeSi NCs in HfO2 multilayered floating gate approach [102], other approach [105] is to use Ge NCs alloyed with both Sn and Si. So, using storage nodes of SiGeSn is advantageous due to the low thermal budget for NCs formation by Sn presence, thus improving the suitability of NVM fabrication in terms of CMOS compatibility, at the same time with ensuring high stability by alloying with little Si.…”
Section: Charge Storage Propertiesmentioning
confidence: 99%
“…If the value is below this, the process of direct tunneling of the charge carriers between the Si substrate and the floating gate layer through the SiO 2 tunneling layer leads to a high-leakage current and a low-charge retention capability of the MOS-like capacitor [4]. A solution to this problem is to replace the SiO 2 with a high-k oxide, such as ZrO 2 , HfO 2 or Al 2 O 3 [5][6][7][8][9][10][11], that has a dielectric constant of k > 20, which is sufficiently high to have a low equivalent oxide thickness (EOT) [12] and low enough to avoid the lateral fringing-field effect [13,14] to be used in MOS-like capacitors. ZrO 2 is characterized by a good interface with Si [15] and being thermally stable [16], and the temperature of the phase transformation from monoclinic to tetragonal is almost 500 • C, which is lower than that for HfO 2 [17,18].…”
Section: Introductionmentioning
confidence: 99%