SiGe vs. Si Selective Wet Etching for Si Gate-all-Around

Komori, Kana; Rip, Jens; Yoshida, Yukifumi; Sebaai, Farid; Liu, Wen Dar; Lee, Yi–Chia; Sekiguchi, Ryo; Mertens, Hans; Hikavyy, Andriy; Holsteyns, Frank; Horiguchi, N.

doi:10.4028/www.scientific.net/ssp.282.107

Cited by 13 publications

(6 citation statements)

References 5 publications

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“…Copper has been replacing aluminum as a BEOL interconnecting metal material for over 20 years. However, copper interconnection faces many difficulties in balancing line resistance (line R) and reliability for advanced technology nodes [289]. Some strategies have been investigated to improve via and line resistance as well as reliability at small dimensions [290].…”

Section: Metal Materials Interconnectmentioning

confidence: 99%

“…The concentration of Mn in the CuMn target material can vary between 0.5% and 10%; the final concentration value depends on a comprehensive evaluation of the line resistance and reliability [296]. Nogami et al believed PVD/ALD TaN and/or tCoSFB as a viable solution to continue scaling barrier/wetting layers, and the interconnection resistance of metals such as cobalt and ruthenium will be better than that of copper due to the limitation of the reduced thickness of the barrier layer in the 5 nm technology node [289].…”

Section: Metal Materials Interconnectmentioning

confidence: 99%

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CMOS Scaling for the 5 nm Node and Beyond: Device, Process and Technology

Radamson,

Miao,

Zhou

et al. 2024

Nanomaterials

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After more than five decades, Moore’s Law for transistors is approaching the end of the international technology roadmap of semiconductors (ITRS). The fate of complementary metal oxide semiconductor (CMOS) architecture has become increasingly unknown. In this era, 3D transistors in the form of gate-all-around (GAA) transistors are being considered as an excellent solution to scaling down beyond the 5 nm technology node, which solves the difficulties of carrier transport in the channel region which are mainly rooted in short channel effects (SCEs). In parallel to Moore, during the last two decades, transistors with a fully depleted SOI (FDSOI) design have also been processed for low-power electronics. Among all the possible designs, there are also tunneling field-effect transistors (TFETs), which offer very low power consumption and decent electrical characteristics. This review article presents new transistor designs, along with the integration of electronics and photonics, simulation methods, and continuation of CMOS process technology to the 5 nm technology node and beyond. The content highlights the innovative methods, challenges, and difficulties in device processing and design, as well as how to apply suitable metrology techniques as a tool to find out the imperfections and lattice distortions, strain status, and composition in the device structures.

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Section: Metal Materials Interconnectmentioning

confidence: 99%

Section: Metal Materials Interconnectmentioning

confidence: 99%

CMOS Scaling for the 5 nm Node and Beyond: Device, Process and Technology

Radamson,

Miao,

Zhou

et al. 2024

Nanomaterials

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“…Indeed, relaxation of the Si1-xGex layer must be avoided as the presence of threading dislocations in the Si-cap has a detrimental effect on electrical properties and on the yield of the devices fabricated afterwards (4). On the other hand, the Ge concentration in the Si1-xGex layer should be sufficiently high to guarantee etch selectivity with respect to the underlying Si substrate (5). In addition, the thickness of the Si1-xGex layer needs to be well chosen taking eventual material loss during Si backside etching into account.…”

Section: Introductionmentioning

confidence: 99%

“…6 On the other hand, the Ge concentration in the Si 1−x Ge x layer should be sufficiently high to guarantee etch selectivity with respect to the underlying Si substrate. 7 In addition, the thickness of the Si 1−x Ge x layer needs to be well chosen taking eventual material loss during Si backside etching into account. Etching of the Si-cap layer during wafer back-side thinning must be prevented.…”

mentioning

confidence: 99%

Epitaxial Growth of Active Si on Top of SiGe Etch Stop Layer in View of 3D Device Integration

et al. 2020

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We describe challenges of the epitaxial Si-cap / Si0.75Ge0.25 // Si-substrate growth process, in view of its application in 3D device integration schemes using Si0.75Ge0.25 as backside etch stop layer with a focus on high throughput epi processing without compromising material quality. While fully strained Si0.75Ge0.25 with a thickness >10 times larger than the theoretical thickness for layer relaxation can be grown, it is challenging to completely avoid misfit dislocations at the wafer edge during Si-capping, even for thinner Si0.75Ge0.25 layers. Extremely sensitive characterization methods are mandatory to detect the extremely low density of misfit dislocations at the wafer edge. Light scattering measurements are most reliable. The epitaxial Si-cap / Si0.75Ge0.25 // Si-substrate layer stacks are stable against post-epi thermal processing steps, typically applied before wafer to wafer bonding and Si-substrate and Si0.75Ge0.25 backside removal.

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“…The latter offers an advantage over the former because its gate can tune the channel more accurately [4]. Some processes used for the fabrication of these complex 3D features used in most advanced FET transistors and memory cells require extremely selective and isotropic etchants [5, 6].…”

Section: Introductionmentioning

confidence: 99%

Scaled-Down c-Si and c-SiGe Wagon-Wheels for the Visualization of the Anisotropy and Selectivity of Wet-Chemical Etchants

et al. 2019

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Wet etching offers an advantage as a soft, damage-less method to remove sacrificial material with close to nanometer precision which has become critical for the fabrication of nanoscale structures. In order to develop such wet etching solutions, screening of etchant properties like selectivity and (an)isotropy has become vital. Since these etchants typically have low etch rates, sensitive test structures are required to evaluate their etching behavior. Therefore, scaled-down single-crystalline Si (c-Si) and SiGe (c-SiGe) wagon-wheels were fabricated. First, the sensitivity of the c-Si wagon-wheels to detect anisotropic behavior of crystalline silicon in the alkaline etchants TMAH and NH 4 OH was demonstrated. Distinctive wagon-wheel patterns, characteristic for each material/etchant pair, were observed by top-down scanning electron microscopy (SEM) after anisotropic wet etching. Similar trends in crystallographic plane-dependent etch rates were obtained for both Si(100) and Si(110) substrates. Secondly, the etching of both c-Si and c-Si 75 Ge 25 wagon-wheels in a typical selective etchant, peracetic acid (PAA), was evaluated. c-Si 75 Ge 25 etching in PAA resulted in isotropic etching. Selectivity values were calculated based on two methods: the first by measurement of the sidewall loss of the spokes of the wagon-wheel, the second, indirect method, through measurement of the spoke retraction lengths. Both methods give comparable values, but the latter method can only be used after a certain critical etching time, after which the spoke tips have evolved toward a sharp tip. Electronic supplementary material The online version of this article (10.1186/s11671-019-3114-8) contains supplementary material, which is available to authorized users.

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SiGe vs. Si Selective Wet Etching for Si Gate-all-Around

Cited by 13 publications

References 5 publications

CMOS Scaling for the 5 nm Node and Beyond: Device, Process and Technology

CMOS Scaling for the 5 nm Node and Beyond: Device, Process and Technology

Epitaxial Growth of Active Si on Top of SiGe Etch Stop Layer in View of 3D Device Integration

Scaled-Down c-Si and c-SiGe Wagon-Wheels for the Visualization of the Anisotropy and Selectivity of Wet-Chemical Etchants

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