SIERRA: a 3-D device simulator for reliability modeling

Chern, Jue-Hsien; Maeda, J.T.; Arledge, L.A.; Yang, Ping

doi:10.1109/43.24880

Cited by 32 publications

(7 citation statements)

References 26 publications

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“…Fully 3-D device simulators were first reported in the literature in the early 1980s [140], and some of the early work on 3-D device simulation was motivated by alpha-particle reliability issues [141], [142]. An early comparison of 2-D and 3-D charge-collection simulations showed that while the transient responses were qualitatively similar, significant quantitative differences existed, both in the magnitude of the current response and the time scale over which collection was observed [143].…”

Section: B Multidimensional Device Simulationsmentioning

confidence: 99%

Basic mechanisms and modeling of single-event upset in digital microelectronics

Dodd

Massengill

2003

IEEE Trans. Nucl. Sci.

896

427

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Physical mechanisms responsible for nondestructive single-event effects in digital microelectronics are reviewed, concentrating on silicon MOS devices and integrated circuits. A brief historical overview of single-event effects in space and terrestrial systems is given, and upset mechanisms in dynamic random access memories, static random access memories, and combinational logic are detailed. Techniques for mitigating single-event upset are described, as well as methods for predicting device and circuit single-event response using computer simulations. The impact of technology trends on single-event susceptibility and future areas of concern are explored.

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Section: B Multidimensional Device Simulationsmentioning

confidence: 99%

Basic mechanisms and modeling of single-event upset in digital microelectronics

Dodd

Massengill

2003

IEEE Trans. Nucl. Sci.

896

427

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“…The matrix calculation to obtain the potential solution is carried out by the ILU-CGS method. 12 The method is very fast and effective in solving an asymmetric matrix. The tolerance was set to 10 Ϫ8 .…”

Section: E Sequence Of the Simulatormentioning

confidence: 99%

Numerical analysis on field emission for the effects of the gate insulators

Ahn

Lee

1995

Journal of Vacuum Science &Amp; Technology B: Microelectronics and Nanometer Structures Processing, Measurement, and Phenomena

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Articles you may be interested inDisplacement current analysis of carrier behavior in pentacene field effect transistor with poly(vinylidene fluoride and tetrafluoroethylene) gate insulator Hole trapping phenomena in the gate insulator of As-fabricated insulated gate field effect transistors A program to solve the Poisson equation by a finite element method has been developed to simulate accurately the distributions of potential and electric field of the field emission microtriode. The emission current can be calculated by this method more accurately and efficiently than the finite difference method. Moreover, we can consider the effect of a gate insulator structure that cannot be treated by boundary element method. The optimal gate insulator is investigated from the viewpoint of the multilayer structure and the edge shape of the insulator. The emission current can be improved more than 85% using a gate insulator with a vertical edge shape and double-layer structure with different permittivities.

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“…It is interesting to compare the EMA with other algorithms which solve directly the linear system resulting from FD discretization. For such a comparison we have chosen the iterative CGS algorithm [14] which exhibits O(n 1.5 ) complexity in applications to band matrices resulting from FD discretization and has a low, O(n) memory requirements. Non-iterative methods of complexity O(n 1.5 ) also exist [13], but they tend to have bigger memory consumption.…”

Section: Performance Of the Edge Moving Algorithmmentioning

confidence: 99%

Modeling of VLSI RC parasitics based on the network reduction algorithm

Niewczas

Wojtasik

1995

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

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This paper presents a method of modeling of R and C parasitics in VLSI circuits. A network representation is generated for finite difference discretization of 2D Laplace's equation, and a reduction algorithm is applied to this network. The solution area can be defined by any set of polygons. The new algorithm, which is O(n 1.5), yields directly the coefficients of capacitance or admittance matrix. In contrast to other methods, in the network reduction approach the time required for modeling depends mainly upon the complexity of the solution area but weakly upon the number of terminals. This feature is particularly valuable in application to circuit extraction.

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SIERRA: a 3-D device simulator for reliability modeling

Cited by 32 publications

References 26 publications

Basic mechanisms and modeling of single-event upset in digital microelectronics

Basic mechanisms and modeling of single-event upset in digital microelectronics

Numerical analysis on field emission for the effects of the gate insulators

Modeling of VLSI RC parasitics based on the network reduction algorithm

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