SIDECAR low-power control ASIC for focal plane arrays including A/D conversion and bias generation

Loose, Markus; Lewyn, L.L.; Durmus, Hakan; Garnett, James D.; Hall, Donald N. B.; Joshi, Atul; Kozlowski, Lester J.; Ovsiannikov, Ilia

doi:10.1117/12.462601

Cited by 23 publications

(7 citation statements)

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“…The minimum spacing between the active area of two arrays must be 2.65 mm at least, or 147 pixels. The area required for the fan-out board serving all four detectors is estimated to be 8 cm x 8 cm which is larger than the area provided for the four SIDECAR ASIC's of the JWST module and slightly larger than the area of the detector mosaic but should still fit into the space envelope of the GL Scientific package foreseen for the ASIC's [9].…”

Section: Introductionmentioning

confidence: 89%

Performance of large-format 2Kx2K MBE-grown HgCdTe Hawaii-2RG arrays for low-flux applications

Finger¹,

Dorn²,

Meyer³

et al. 2004

SPIE Proceedings

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VLT instruments increasingly require high sensitivity large format focal planes. Adaptive optics combined with multiple integral field units feeding high resolution spectrographs drive the pixel performance as well as the array format. Three VLT instruments, the wide field imager Hawk-I [1]and the integral field spectrographs SINFONI [2] and KMOS [3] will be equipped with MBE-grown HgCdTe Hawaii-2RG arrays, which have a cut-off wavelength of 2.5 micron. The Hawaii-2RG array was originally developed for the near infrared camera of JWST having a cut-off wavelength of 5 micron [4].The Hawaii-2RG multiplexer is one of the most advanced readout architectures offering a large variety of operating modes. A special 32 channel package has been developed which allows reading out all 32 output channels of the detector in parallel [7]. Symmetric cryogenic CMOS operational amplifiers are placed next to the focal plane instead of using ASIC's which are not yet available. The internal bus of the detector is accessed directly, bypassing the on-chip buffer amplifier. Noise performance employing different techniques of using reference pixels is discussed. Basic performance characteristics of the Hawaii-2RG arrays will be presented. Unlike LPE arrays, which lose quantum efficiency at lower temperatures, MBE arrays with λ c =2.5 µm do not show this effect. However, the MBE arrays under test still suffer from persistence.Keywords: infrared detector, Hawaii-2RG, HgCdTe, readout noise, dark current, quantum efficiency, persistence Set-upBecause of stringent power limitations on JWST, which is one application for the Hawaii2-RG detectors, only four channels of the array are read out in parallel resulting in a minimum integration time of 41 seconds. This readout time is too long for ground based applications. For this reason a joint effort was made by Gemini, Keck, CFHT and ESO to fund GL Scientific to develop the 32-channel detector package interfacing all 32 video channels of the Hawaii-2RG multiplexer. The backside of the 32-channel detector package is shown in Figure 1 with the flex board mounted on the PGA [7]. At the end of the flex board there is a 92 pin HIROSE connector for electrical interfacing. The array is *

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Section: Introductionmentioning

confidence: 89%

Performance of large-format 2Kx2K MBE-grown HgCdTe Hawaii-2RG arrays for low-flux applications

Finger¹,

Dorn²,

Meyer³

et al. 2004

SPIE Proceedings

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“…Since the detector multiplexers are based on standard CMOS processes then the addition of the external detector control electronics onto the detector itself will be especially welcome. There is already a move in this direction with the SIDECAR ASIC [6] produced by Rockwell to operate their HAWAII-2RG detector. To reduce development risks this ASIC has been designed external to the multiplexer and is mounted beside the detector.…”

Section: The Future For Ir Detectorsmentioning

confidence: 97%

Large area near infra-red detectors for astronomy

Ives

Bezawada

2007

Nuclear Instruments and Methods in Physics Research Section A:

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“…The first one is an analog image sensor, like the one used with discrete electronics controllers. The second chip is a programmable mixed-signal ASIC that effectively combines all functions of the discrete controller in a single chip Loose et al (2003). The two chips together form a small and lightweight, yet flexible and high-performance, camera system.…”

Section: Cmos-based Detector Systemsmentioning

confidence: 99%

CMOS Detector Technology

2006

Self Cite

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An entry level overview of state-of-the-art CMOS detector technology is presented. Operating principles and system architecture are explained in comparison to the well-established CCD technology, followed by a discussion of important benefits of modern CMOS-based detector arrays. A number of unique CMOS features including different shutter modes and scanning concepts are described. In addition, sub-field stitching is presented as a technique for producing very large imagers. After a brief introduction to the concept of monolithic CMOS sensors, hybrid detectors technology is introduced. A comparison of noise reduction methods for CMOS hybrids is presented. The final sections review CMOS fabrication processes for monolithic and vertically integrated image sensors.

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SIDECAR low-power control ASIC for focal plane arrays including A/D conversion and bias generation

Cited by 23 publications

References 0 publications

Performance of large-format 2Kx2K MBE-grown HgCdTe Hawaii-2RG arrays for low-flux applications

Performance of large-format 2Kx2K MBE-grown HgCdTe Hawaii-2RG arrays for low-flux applications

Large area near infra-red detectors for astronomy

CMOS Detector Technology

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