Side-Channel Leakage of Masked CMOS Gates

Mangard, Stefan; Popp, Thomas; Gammel, Berndt M.

doi:10.1007/978-3-540-30574-3_24

Cited by 236 publications

(177 citation statements)

References 21 publications

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“…Its main drawback is that the performance overheads can be important because of the need to compute a correction term on-the-fly, during the encryption process. Masking can be defeated by higher-order attacks [21] or because of technological issues such as glitches [18]. Overall, it is usually considered as one useful part of the solution for protecting cryptographic hardware.…”

Section: Related Workmentioning

confidence: 99%

Fresh Re-keying: Security against Side-Channel and Fault Attacks for Low-Cost Devices

Medwed

Standaert

Großschädl

et al. 2010

Lecture Notes in Computer Science

101

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The market for RFID technology has grown rapidly over the past few years. Going along with the proliferation of RFID technology is an increasing demand for secure and privacy-preserving applications. In this context, RFID tags need to be protected against physical attacks such as Differential Power Analysis (DPA) and fault attacks. The main obstacles towards secure RFID are the extreme constraints of passive tags in terms of power consumption and silicon area, which makes the integration of countermeasures against physical attacks even more difficult than for other types of embedded systems. In this paper we propose a fresh re-keying scheme that is especially suited for challenge-response protocols such as used to authenticate tags. We evaluate the resistance of our scheme against fault and side-channel analysis, and introduce a simple architecture for VLSI implementation on RFID tags. In addition, we estimate the cost of our scheme in terms of area and execution time for various sec... Abstract. The market for RFID technology has grown rapidly over the past few years. Going along with the proliferation of RFID technology is an increasing demand for secure and privacy-preserving applications. In this context, RFID tags need to be protected against physical attacks such as Differential Power Analysis (DPA) and fault attacks. The main obstacles towards secure RFID are the extreme constraints of passive tags in terms of power consumption and silicon area, which makes the integration of countermeasures against physical attacks even more difficult than for other types of embedded systems. In this paper we propose a fresh re-keying scheme that is especially suited for challenge-response protocols such as used to authenticate tags. We evaluate the resistance of our scheme against fault and side-channel analysis, and introduce a simple architecture for VLSI implementation on RFID tags. In addition, we estimate the cost of our scheme in terms of area and execution time for various security/performance trade-offs. Our experimental results show that the proposed re-keying scheme provides better security (and does so at less cost) than other state-of-the-art countermeasures.

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Section: Related Workmentioning

confidence: 99%

Fresh Re-keying: Security against Side-Channel and Fault Attacks for Low-Cost Devices

Medwed

Standaert

Großschädl

et al. 2010

Lecture Notes in Computer Science

101

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“…For example, Mangard pointed out that the countermeasure to implement random masking by combinational circuit [2] should leak out the secret information from the power consumption caused due to glitches [3] and actually, they found DPA leakage on the real ASIC [4]. Random Switching Logic (RSL) [5] proposed by Suzuki et al can suppress the occurrence of glitch and make uniform the power consumption at each gate in the statistical analysis using the random number.…”

Section: Introductionmentioning

confidence: 99%

Security Evaluation of DPA Countermeasures Using Dual-Rail Pre-charge Logic Style

Suzuki

Saeki

2006

Lecture Notes in Computer Science

115

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Abstract. In recent years, some countermeasures against Differential Power Analysis (DPA) at the logic level have been proposed. At CHES 2005 conference, Popp and Mangard proposed a new countermeasure named Masked Dual-Rail Pre-Charge Logic (MDPL) which combine dual-rail circuits with random masking to improve Wave Dynamic Differential Logic (WDDL). The proposers of MDPL claim that it can implement secure circuits using a standard CMOS cell library without special constraints for the place-and-route because the difference of loading capacitance between all pairs of complementary logic gates in MDPL can be covered up by the random masking. In this paper, we especially focus the signal transition of the MDPL gate and evaluate the DPA-resistance of MDPL in detail. Our evaluation results show that the leakage occurs in the MDPL gates as well as WDDL gates when input signals have difference of delay time even if MDPL has an effectiveness on reducing the leakage caused by the difference of loading capacitance. Furthermore, we demonstrate the problem with different input signal delays by measurements of an FPGA and show the validity of our evaluation.

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“…Although these methods have been originally applied at the algorithmic level as well as at the gate level, it has been shown recently that masking at the gate level involves critical security concerns. Reference [10] notably demonstrates that the glitching activity of masked logic gates offers a previously neglected leakage source that seriously affects the security of the countermeasure. For this reason, this paper will mainly discuss the algorithmic level protection, using precomputed tables.…”

Section: The Masking Countermeasurementioning

confidence: 99%

Improved Higher-Order Side-Channel Attacks with FPGA Experiments

Peeters

Standaert

Donckers

et al. 2005

Cryptographic Hardware and Embedded Systems – CHES 2005

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Abstract. We demonstrate that masking a block cipher implementation does not sufficiently improve its security against side-channel attacks. Under exactly the same hypotheses as in a Differential Power Analysis (DPA), we describe an improvement of the previously introduced higherorder techniques allowing us to defeat masked implementations in a low (i.e. practically tractable) number of measurements. The proposed technique is based on the efficient use of the statistical distributions of the power consumption in an actual design. It is confirmed both by theoretical predictions and practical experiments against FPGA devices.

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Side-Channel Leakage of Masked CMOS Gates

Cited by 236 publications

References 21 publications

Fresh Re-keying: Security against Side-Channel and Fault Attacks for Low-Cost Devices

Fresh Re-keying: Security against Side-Channel and Fault Attacks for Low-Cost Devices

Security Evaluation of DPA Countermeasures Using Dual-Rail Pre-charge Logic Style

Improved Higher-Order Side-Channel Attacks with FPGA Experiments

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