Side-channel leakage aware instruction scheduling

Seuschek, Hermann; Santis, Fabrizio De; Guillen, Oscar M.

doi:10.1145/3031836.3031838

Cited by 10 publications

(10 citation statements)

References 12 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…For example, it was shown in [16] that a masked hardware implementation of the AES can be broken by exploiting glitches at the outputs of logic gates. On the other hand, software implementations of masked ciphers can also be vulnerable to DPA attacks because of unintended violations of the independent leakage requirement mentioned above, typically caused by certain micro-architectural effects and features [4,18,21]. Therefore, it is important to check whether a masked implementation meets its theoretical security promises also in practice (i.e.…”

Section: Introductionmentioning

confidence: 99%

Micro-architectural Power Simulator for Leakage Assessment of Cryptographic Software on ARM Cortex-M3 Processors

Corre

Großschädl

Dinu

2018

Lecture Notes in Computer Science

View full text Add to dashboard Cite

Masking is a common technique to protect software implementations of symmetric cryptographic algorithms against Differential Power Analysis (DPA) attacks. The development of a properly masked version of a block cipher is an incremental and time-consuming process since each iteration of the development cycle involves a costly leakage assessment. To achieve a high level of DPA resistance, the architecturespecific leakage properties of the target processor need to be taken into account. However, for most embedded processors, a detailed description of these leakage properties is lacking and often not even the HDL model of the micro-architecture is openly available. Recent research has shown that power simulators for leakage assessment can significantly speed up the development process. Unfortunately, few such simulators exist and even fewer take target-specific leakages into account. To fill this gap, we present MAPS, a micro-architectural power simulator for the M3 series of ARM Cortex processors, one of today's most widely-used embedded platforms. MAPS is fast, easy to use, and able to model the Cortex-M3 pipeline leakages, in particular the leakage introduced by the pipeline registers. The M3 leakage properties are inferred from its HDL source code, and therefore MAPS does not need a complicated and expensive profiling phase. Taking first-order masked Assembler implementations of the lightweight cipher Simon as example, we study how the pipeline leakages manifest and discuss some guidelines on how to avoid them.

show abstract

Section: Introductionmentioning

confidence: 99%

Micro-architectural Power Simulator for Leakage Assessment of Cryptographic Software on ARM Cortex-M3 Processors

Corre

Großschädl

Dinu

2018

Lecture Notes in Computer Science

View full text Add to dashboard Cite

show abstract

“…In [18,19], the authors prove that the computing platform reveals information on the Hamming distance between the contents of two independent destination registers of two subsequent instructions due to register file write-port sharing. This leakage (from an ISA point-of-view) breaks provably secure countermeasure schemes implemented with state of the art assembly code [18].…”

Section: Background and Related Workmentioning

confidence: 99%

“…This is usually done since micro-architectural level specification of CPUs may not be freely available or known. However, two works sharing our research direction [18,19] show unexpected leakage behaviors from software block ciphers implemented on an a AVR 8bit microcontroller explainable only with a more detailed execution model. In [18,19], the authors prove that the computing platform reveals information on the Hamming distance between the contents of two independent destination registers of two subsequent instructions due to register file write-port sharing.…”

Section: Background and Related Workmentioning

confidence: 99%

“…However, two works sharing our research direction [18,19] show unexpected leakage behaviors from software block ciphers implemented on an a AVR 8bit microcontroller explainable only with a more detailed execution model. In [18,19], the authors prove that the computing platform reveals information on the Hamming distance between the contents of two independent destination registers of two subsequent instructions due to register file write-port sharing. This leakage (from an ISA point-of-view) breaks provably secure countermeasure schemes implemented with state of the art assembly code [18].…”

Section: Background and Related Workmentioning

confidence: 99%

See 1 more Smart Citation

Side-channel security of superscalar CPUs

Barenghi

Pelosi

2018

Proceedings of the 55th Annual Design Automation Conference

View full text Add to dashboard Cite

Side-channel attacks are performed on increasingly complex targets, starting to threaten superscalar CPUs supporting a complete operating system. The difficulty of both assessing the vulnerability of a device to them, and validating the effectiveness of countermeasures is increasing as a consequence. In this work we prove that assessing the side-channel vulnerability of a software implementation running on a CPU should take into account the microarchitectural features of the CPU itself. We characterize the impact of microarchitectural features and prove the effectiveness of such an approach attacking a dual-core superscalar CPU. CCS CONCEPTS• Security and privacy → Embedded systems security; Sidechannel analysis and countermeasures;

show abstract

“…Seuschek et al [SSG17] suggest use of leakage aware code generation [SSG17,Section 6]. This involves careful 1) scheduling (i.e., ordering) of instructions, and 2) register allocation informed by a leakage characterisation [SSG17, Section 4] which captures vulnerable instruction sequences.…”

Section: Countermeasuresmentioning

confidence: 99%

FENL: an ISE to mitigate analogue micro-architectural leakage

Gao

Marshall

Page

et al. 2020

TCHES

View full text Add to dashboard Cite

Ge et al. [GYH18] propose the augmented ISA (or aISA), a central tenet of which is the selective exposure of micro-architectural resources via a less opaque abstraction than normal. The aISA proposal is motivated by the need for control over such resources, for example to implement robust countermeasures against microarchitectural attacks. In this paper, we apply an aISA-style approach to challenges stemming from analogue micro-architectural leakage; examples include power-based Hamming weight and distance leakage from relatively fine-grained resources (e.g., pipeline registers), which are not exposed in, and so cannot be reliably controlled via, a normal ISA. Specifically, we design, implement, and evaluate an ISE named FENL: the ISE acts as a fence for leakage, preventing interaction between, and hence leakage from, instructions before and after it in program order. We demonstrate that the implementation and use of FENL has relatively low overhead, and represents an effective tool for systematically localising and reducing leakage.

show abstract

Side-channel leakage aware instruction scheduling

Cited by 10 publications

References 12 publications

Micro-architectural Power Simulator for Leakage Assessment of Cryptographic Software on ARM Cortex-M3 Processors

Micro-architectural Power Simulator for Leakage Assessment of Cryptographic Software on ARM Cortex-M3 Processors

Side-channel security of superscalar CPUs

FENL: an ISE to mitigate analogue micro-architectural leakage

Contact Info

Product

Resources

About