Side-channel analysis of a learning parity with physical noise processor

Kamel, Dina; Bellizia, Davide; Bronchain, Olivier; Standaert, François‐Xavier

doi:10.1007/s13389-020-00238-3

Cited by 4 publications

(8 citation statements)

References 24 publications

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“…Maximum peaks of SNR for each bit are reported in Figure 11A and their average values are in Figure 11B. These figures show similar trends as for the ASIC prototype in [KBBS20]. Namely, the best SNR is observed for the initial AND gate, while digging through the inner product computations first reduces this SNR before increasing it.…”

Section: Conclusion and Further Researchsupporting

confidence: 59%

“…A side-channel evaluation of the FPGA processor is also given in Appendix C. It estimates the sidechannel Signal-to-Noise Ratio (SNR) of different target intermediate computations in the different (AND and XOR) stages of the LPPN processor [Man04]. Those results confirm the ASIC ones in [KBBS20] and show that the best targets are the AND stage and the last XOR stage, both of them exhibiting quite low SNRs though (in the 10 −5 range).…”

Section: Functional (And Other) Validation(s)mentioning

confidence: 57%

“…In this last case, we refer to the SNR values given in Appendix C which are in the 10 −5 range. 8 Given that (i) the data complexity of a side-channel attack against a target intermediate computation is inversely proportional to the SNR, and (ii) the attack against the incorrect shared inner product that we target is an SPA, we can directly conclude that the δ value of Section 5 will be close to 1 2 in our case (e.g., it is lower than the success rate for n = 1 estimated in [KBBS20] which exhibits larger SNR values). As a result, the security of the (masked) LPPN samples will be close to the one of LPN samples.…”

Section: Putting Things Togethermentioning

confidence: 71%

“…Besides the fact that such a masking improves security against Differential Power Analysis (DPA), as discussed in [KBBS20], it also reduces the ∆ of the corresponding LPN-OD problem as follows. First, assume that the incorrect computation of z indeed suffers from output data dependencies of the error probability such that Pr[e = 1| x, k 1 = 0] = 0 and Pr[e = 1 | x, k 1 = 1] = 1 .…”

Section: Masked Lppnmentioning

confidence: 99%

“…They formalized the corresponding problem as the Learning with Physical Noise (LPPN) problem, and highlighted its potential advantages in terms of implementation cost (since it removes the need to explicitly generate randomness for the additive errors) and implementation security (since it prevents the trivial attack probing the randomness in a leaking implementation). A first ASIC prototype of LPPN processor was then described in [KBS + 18] and its side-channel security has been evaluated in [KBBS20]. Nevertheless, and despite these promising and quite unique features, the understanding of the security and applicability of LPPN remains limited.…”

Section: Introductionmentioning

confidence: 99%

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Learning Parity with Physical Noise: Imperfections, Reductions and FPGA Prototype

Bellizia

Hoffmann

Kamel

et al. 2021

TCHES

Self Cite

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Hard learning problems are important building blocks for the design of various cryptographic functionalities such as authentication protocols and post-quantum public key encryption. The standard implementations of such schemes add some controlled errors to simple (e.g., inner product) computations involving a public challenge and a secret key. Hard physical learning problems formalize the potential gains that could be obtained by leveraging inexact computing to directly generate erroneous samples. While they have good potential for improving the performances and physical security of more conventional samplers when implemented in specialized integrated circuits, it remains unknown whether physical defaults that inevitably occur in their instantiation can lead to security losses, nor whether their implementation can be viable on standard platforms such as FPGAs. We contribute to these questions in the context of the Learning Parity with Physical Noise (LPPN) problem by: (1) exhibiting new (output) data dependencies of the error probabilities that LPPN samples may suffer from; (2) formally showing that LPPN instances with such dependencies are as hard as the standard LPN problem; (3) analyzing an FPGA prototype of LPPN processor that satisfies basic security and performance requirements.

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Section: Conclusion and Further Researchsupporting

confidence: 59%

Section: Functional (And Other) Validation(s)mentioning

confidence: 57%

Section: Putting Things Togethermentioning

confidence: 71%

Section: Masked Lppnmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

See 3 more Smart Citations

Learning Parity with Physical Noise: Imperfections, Reductions and FPGA Prototype

Bellizia

Hoffmann

Kamel

et al. 2021

TCHES

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Post-Quantum Cryptography: Challenges and Opportunities for Robust and Secure HW Design

Bellizia

Mrabet

Fournaris

et al. 2021

2021 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT)

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Post-Quantum Cryptography (PQC) will become soon the standard for many systems of the future. With the advent of quantum computers, all encrypted communications based on traditional asymmetric cryptography (e.g., RSA, ECC) will become insecure. The definition the PQC standards is an on going process proceeding at a fast pace, involving new and largely unexplored cryptographic primitives. For this reason, the design of hardware implementations of PQC algorithms is still under study. In this paper, we introduce the fundamentals of PQC, with a focus on lattice-based cryptography and its hardware security issues, namely side-channel and fault-based attacks. Then, we focus on isogeny-based cryptography and the SIKE algorithm. We highlight the importance of fault-tolerant design choices through the presentation of a fault attack, based on the electromagnetic injection of transient faults, targeting this cryptographic primitive. Finally, we show an interesting idea that starts from the observation that some PQC algorithms have an intrinsic probabilistic behavior. We argue that this characteristic is a clear opportunity that paves the way for the application of approximate (or inexact) computing to the implementation of PQC cryptography.

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SFGA-CPA: A Novel Screening Correlation Power Analysis Framework Based on Genetic Algorithm

Liu,

Li,

et al. 2024

CMC

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Correlation power analysis (CPA) combined with genetic algorithms (GA) now achieves greater attack efficiency and can recover all subkeys simultaneously. However, two issues in GA-based CPA still need to be addressed: key degeneration and slow evolution within populations. These challenges significantly hinder key recovery efforts. This paper proposes a screening correlation power analysis framework combined with a genetic algorithm, named SFGA-CPA, to address these issues. SFGA-CPA introduces three operations designed to exploit CPA characteristics: propagative operation, constrained crossover, and constrained mutation. Firstly, the propagative operation accelerates population evolution by maximizing the number of correct bytes in each individual. Secondly, the constrained crossover and mutation operations effectively address key degeneration by preventing the compromise of correct bytes. Finally, an intelligent search method is proposed to identify optimal parameters, further improving attack efficiency. Experiments were conducted on both simulated environments and real power traces collected from the SAKURA-G platform. In the case of simulation, SFGA-CPA reduces the number of traces by 27.3% and 60% compared to CPA based on multiple screening methods (MS-CPA) and CPA based on simple GA method (SGA-CPA) when the success rate reaches 90%. Moreover, real experimental results on the SAKURA-G platform demonstrate that our approach outperforms other methods.

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Side-channel analysis of a learning parity with physical noise processor

Cited by 4 publications

References 24 publications

Learning Parity with Physical Noise: Imperfections, Reductions and FPGA Prototype

Learning Parity with Physical Noise: Imperfections, Reductions and FPGA Prototype

Post-Quantum Cryptography: Challenges and Opportunities for Robust and Secure HW Design

SFGA-CPA: A Novel Screening Correlation Power Analysis Framework Based on Genetic Algorithm

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