SI-Studio, a layout generator of current mode circuits

Handkiewicz, Andrzej; Szczęsny, Szymon; Naumowicz, Mariusz; Katarzyński, Piotr; Melosik, Michał; Śniatała, Pawel; Kropidłowski, Marek

doi:10.1016/j.eswa.2014.11.048

Cited by 15 publications

(8 citation statements)

References 18 publications

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“…The distribution for the remaining training parameters (F1, recall and precision) is of a similar nature. The linear, polynomial or exponential dependencies presented in Tables 3-5 are characteristic of CMOS circuits operating in the current mode and were also observed by the authors during their previous research based on 180 nm and 350 nm technologies [12,48]. Only the c a1 ÷ c a21 , c p1 ÷ c p21 and c f 1 ÷ c f 6 parameters are specific to a specific technology.…”

Section: Hardware Complexitysupporting

confidence: 66%

Study of the Complexity of CMOS Neural Network Implementations Featuring Heart Rate Detection

Baryczkowski,

Szczepaniak,

Matykiewicz

et al. 2023

Electronics

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The growing popularity of edge computing goes hand in hand with the widespread use of systems based on artificial intelligence. There are many different technologies used to accelerate AI algorithms in end devices. One of the more efficient is CMOS technology thanks to the ability to control the physical parameters of the device. This article discusses the complexity of the semiconductor implementation of TinyML edge systems in relation to various criteria. In particular, the influence of the model parameters on the complexity of the system is analyzed. As a use case, a CMOS preprocessor device dedicated to detecting heart rate in wearable devices is used. The authors use the current and weak inversion operating modes, which allow the preprocessor to be powered by cells of the human energy harvesting class. This work analyzes the influence of tuning hyperparameters of the learning process on the performance of the final device. This article analyzes the relationships between the model parameters (accuracy and neural network size), input data parameters (sampling rates) and CMOS circuit parameters (circuit area, operating frequency and power consumption). Comparative analyses are performed using TSMC 65 nm CMOS technology. The results presented in this article may be useful to direct this work with the model in terms of the final implementation as the integrated circuit. The dependencies summarized in this work can also be used to initially estimate the costs of the hardware implementation of the model.

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Section: Hardware Complexitysupporting

confidence: 66%

Study of the Complexity of CMOS Neural Network Implementations Featuring Heart Rate Detection

Baryczkowski,

Szczepaniak,

Matykiewicz

et al. 2023

Electronics

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“…This paper, based on the example of SI circuits, demonstrates a novel approach to solving such issues. The method described will be illustrated by the example of filter pair working in SI mode [7,9]. The starting point consists of pre-developed tools to design such circuits [22].…”

Section: Nano-studio Environmentmentioning

confidence: 99%

“…Assuming, comparing the small number samples in time domain allows simultaneous optimization of frequency characteristics and elimination of dc offset. The filter pair referred to above was designed in gC-studio [17] and synthesized by means of SI-studio [9].…”

Section: Nano-studio Environmentmentioning

confidence: 99%

NANO-studio, the design environment of filter banks implemented in standard CMOS technology

Handkiewicz¹,

Naumowicz

2021

Analog Integr Circ Sig Process

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The paper presents a method of optimizing frequency characteristics of filter banks in terms of their implementation in digital CMOS technologies in nanoscale. Usability of such filters is demonstrated by frequency-interleaved (FI) analog-to-digital converters (ADC). An analysis filter present in these converters was designed in switched-current technique. However, due to huge technological pitch of standard digital CMOS process in nanoscale, its characteristics substantially deviate from the required ones. NANO-studio environment presented in the paper allows adjustment, with transistor channel sizes as optimization parameters. The same environment is used at designing a digital synthesis filter, whereas optimization parameters are input and output conductances, gyration transconductances and capacitances of a prototype circuit. Transition between analog s and digital z domains is done by means of bilinear transformation. Assuming a lossless gyrator-capacitor (gC) multiport network as a prototype circuit, both for analysis and synthesis filter banks in FI ADC, is an implementation of the strategy to design filters with low sensitivity to parameter changes. An additional advantage is designing the synthesis filter as stable infinite impulse response (IIR) instead of commonly used finite impulse response (FIR) filters. It provides several dozen-fold saving in the number of applied multipliers.. The analysis and synthesis filters in FI ADC are implemented as filter pairs. An additional example of three-filter bank demonstrates versatility of NANO-studio software.

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“…Both proposed methods make it possible to calculate parameters of the model with values which have counterparts in the lower area of the solution grid, which, in turn, ensures mapping with high accuracy. Calculations can be made automatically using the environment proposed in another work [16]. Below, a snippet of a VHDL-AMS schematic description was added to present the spread of scaling factors and the whole architecture of the filter with a balanced structure.…”

Section: Elliptic Filtermentioning

confidence: 99%

“…The development of reconfigurable analog circuits, especially field-programmable analog arrays (FPAA) is nowadays the most current challenge in the VLSI 1 branch of science which follows the trends of miniaturisation and automation [11,14,16,26,47]. Solutions for implementing large-scale programmable circuits prototypes with parameters comparable to these of dedicated analog circuits have been appearing in the last few years [1,3,22,24,30].…”

Section: Introductionmentioning

confidence: 99%

Current-Mode FPAA with CMRR Elimination and Low Sensitivity to Mismatch

SzczăźSny

2016

Circuits Syst Signal Process

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This article introduces a current-mode field-programmable analog array (FPAA) architecture with its programming methods. The biggest benefit of the proposed approach is solving the problem of implementing reconfigurable analog circuits in modern nanometre technologies. It is achieved thanks to adopting a switched-current (SI) technique which allows to implement the array using transistors based only on the standard digital CMOS technology. The work describes an implementation of a reconfigurable current mirror basing on using a digital-to-analog converter. The article addresses a routing problem of current-mode modules working in a balanced mode. Author proposes methods for CMRR compensation in a huge array architecture. The array was programmed taking into consideration parasitic elements of the layout with the emphasis on topography mismatch. Examples of implementing a 10-bit digital-analog converter, an elliptic filter with SNR = 40.42 dB, 2D-DCT processor with PSNR = 53.05 dB and RGB-to-YCrCb converter with PSNR = 46.95 dB are presented. The elaborated array can be used as IPcore in a larger mixed-signal system or can act as a dedicated circuit.

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SI-Studio, a layout generator of current mode circuits

Cited by 15 publications

References 18 publications

Study of the Complexity of CMOS Neural Network Implementations Featuring Heart Rate Detection

Study of the Complexity of CMOS Neural Network Implementations Featuring Heart Rate Detection

NANO-studio, the design environment of filter banks implemented in standard CMOS technology

Current-Mode FPAA with CMRR Elimination and Low Sensitivity to Mismatch

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