Si–InAs heterojunction Esaki tunnel diodes with high current densities

Abstract

Si–InAs heterojunction p-n diodes were fabricated by growing InAs nanowires in oxide mask openings on silicon substrates. At substrate doping concentrations of 1×1016 and 1×1019 cm−3, conventional diode characteristics were obtained, from which a valence band offset between Si and InAs of 130 meV was extracted. For a substrate doping of 4×1019 cm−3, heterojunction tunnel diode characteristics were obtained showing current densities in the range of 50 kA/cm2 at 0.5 V reverse bias. In addition, in situ doping of the InAs wires was performed using disilane to further boost the tunnel currents up to 100 kA/cm2 at 0.5 V reverse bias for the highest doping ratios.

Growth mechanisms and process window for InAs V-shaped nanoscale membranes on Si[001]

“…For all this to become a reality, detailed studies on the formation mechanisms of novel nanoscale shapes are extremely important. At the same time, there has been a significant effort towards the growth of ordered nanostructures by a combination of top-down and bottom-up processes [26,27], and towards the integration of III-V nanostructures on silicon [28][29][30][31][32][33][34]. The ordered growth of nanostructures on silicon opens many new perspectives as it enables to combine two very powerful platforms.…”

Evaluation of Radio-Frequency Performance of Gate-All-Around Ge/GaAs Heterojunction Tunneling Field-Effect Transistor with Hetero-Gate-Dielectric by Mixed-Mode Simulation

“…These [24]. Combinational uses of plasma laser annealing doping (PLAD), excimer laser annealing (ELA), and dopant profile-steepening implantation (DPSI) can be considered as the most recent possible techniques to obtain high doping concentration with nearly abrupt junctions [25][26][27].…”

Bottom-up engineering of InAs at the nanoscale: From V-shaped nanomembranes to nanowires

“…The last few years have also seen an increased interest in III-V materials and in the integration of III-Vs on silicon which is facilitated by nanowires [25][26][27][28][29][30][31]. Nanoscale electronics, optoelectronics, photonics and photovoltaics would benefit from this integration because nanoscale structures could be eventually engineered on silicon, a mature and less expensive platform and with complementary functionality.…”

“…Silicon (001) is the platform in use across the microelectronics industry, as CMOS fabrication on [110] reduction of structural defects and suppression of polytypism [35,36]. The ordered growth of III-V nanostructures has been intensively studied very recently in different material systems [26,35,[37][38][39][40][41][42][43][44]. Different techniques such as electron beam, nanosphere, nanoimprint or phase-shift lithography have been used for the definition of the patterns [45][46][47][48][49][50].…”