Shrinkable Triple Self-Aligned Field-Enhanced Split-Gate Flash Memory

Abstract

This paper demonstrates a shrinkable triple self-aligned split-gate Flash cell fabricated using a standard 0.13-mcopper interconnect process. The approach used here to create a self-aligned structure is to form a spacer against the prior layer. Due to a higher aspect ratio when the cell pitch decreases, the profile of the spacer structure becomes sharper. This improves process control of the spacer profile and length. All the processes used here are compatible with standard logic process. The word line channel length of the cell is 0.11 m. It is comparable in area with a stacked-gate cell and can be less than 13F 2 . The cell is erased by using poly-poly Fowler-Nordheim tunneling with a sharp floating-gate edge to increase the electric field, and is programmed by source-side injection. As a result, this cell is highly suitable for low power applications and embedded products. Characterization shows considerable program and erase speed, up to 300 K times cycling endurance, and excellent disturb margins.

Erase voltage impact on 0.18 μm triple self-aligned split-gate flash memory endurance

“…The phenomenon that lower V ERS causes more I r1 degradation has been explained in Ref. [12]. After P/E cycling, electrons trapped in the tunnel oxide cause erase efficiency drop and subsequent FG potential drop, which has a similar effect to applying a lower erase voltage.…”

Enhance the split-gate flash cell performance by partially decoupling the SG oxide thickness from the tunnel oxide thickness

“…The method is demonstrated in this paper by flash cells fabricated mainly by the 0.18 lm triple self-aligned split-gate flash method [5,6]. The FG oxide is thermal grown with a thickness of 9 nm.…”

“…Among different split-gate memory cells, the self-aligned split-gate flash cell has attracted much research interest for its fast erase, modular process and compatibility to CMOS process [5][6][7][8][9][10]. It uses floating gate (FG) tip enhanced poly-to-poly (FG to select gate) F-N tunnelling for erase, and source side hot electron injection for program [11,12].…”

A novel high-density embedded AND-type split gate flash memory

“…[4][5][6][7][8][9] Among various technologies of flash memory, split gate flash memory using source-side-enhanced hot-electron injection with high programming efficiency and tip structures to improve the local electric field is very popular for embedded systems. [10][11][12][13][14] To meet its customized requirement, such as those for mobile or automotive application, the optimization of processes has been extensively discussed. [15][16][17][18][19][20][21][22][23][24][25] Recently, the development of the split gate has focused on a 3-poly structure, which has the advantages of low power and high coupling ratio.…”