Short circuit faults in state-of-the-art ADCs - are they hard or soft?

Flexible embedded test solution for high-speed analogue front-end architectures

“…For the representative design, with f S ¼ 330 MHz, OS ¼ 1 LSB and CC ideal ¼ 8, the test time for a single ramp stimulus results to 1.6 ms. Failure mode detection capabilities have been assessed through simulation. Typical failure modes, some of which are discussed in [31], were modelled within the input stimuli to the ideal converter model. Figure 12 illustrates the code count sequence, DNL and INL computation for a converter suffering from nonlinearity in the centre of its input range.…”

“…The results of testability analyses performed on representative analogue front-end components [28,31] and the interpretation of these for other high-speed architectures [32] provides evidence for superior test quality compared to conventional FFT-based testing. The kernel test time for the programmable gain block is reduced significantly while more time-consuming data capturing is avoided in A/D converter testing.…”

“…In this particular case, the flexible embedded test solution has been designed for an analogue front-end containing a 32-gain-set automatic gain control circuit and a 6-bit A/D converter. Details of the analogue front-end originally analysed in [28,31] and the designed test solution are listed in Table 1. Apart from the indication of window overflow discussed above, the designed circuitry also indicates overflow in DNL and INL computation and allows test application for both rising and falling ramp stimulus sections.…”

“…An additional testability analysis has been performed on a 6-bit folding and interpolating A/D converter. Its failure modes and test requirements are described in [31], where the severity of failure modes is analysed in terms of static and dynamic performance parameters. This particular architecture was chosen, as it allows conclusions to be drawn on the test requirements of other high-speed architectures, such as full-flash, folding, interpolating and subranging A/D converters that may or may not include internal offset compensating resistor ladders at differential amplifier outputs [32].…”