Short Channel Analytical Model for High Electron Mobility Transistor to Obtain Higher Cut-Off Frequency Maintaining the Reliability of the Device

Abstract

Abstract-A comprehensive short channel analytical model has been proposed for High Electron Mobility Transistor (HEMT) to obtain higher cut-off frequency maintaining the reliability of the device. The model has been proposed to consider generalized doping variation in the directions perpendicular to and along the channel. The effect of field plates and different gate-insulator geometry (Tgate, etc) have been considered by dividing the area between gate and the high band gap semiconductor into different regions along the channel having different insulator and metal combinations of different thicknesses and work function with the possibility that metal is in direct contact with the high band gap semiconductor. The variation obtained by gate-insulator geometry and field plates in the field and channel potential can be produced by varying doping concentration, metal workfunction and gate-stack structures along the channel. The results so obtained for normal device structure have been compared with previous proposed model and numerical method (finite difference method) to prove the validity of the model.

Metal Insulator Gate Geometric HEMT: Novel Attributes and Design Consideration for High Speed Analog Applications

“…2 to obtain the resultant capacitance for various metalinsulator geometries under consideration. Using the drain current model evaluated in the above section, gatesource capacitance and gate-drain capacitance is calculated in various regions and is given by [30,[32][33][34] and 3 5 3 3 2 2 4 2 2 1 4…”

“…Generalized analytical model for HEMT [30,[32][33][34] has been used to obtain the analytical results. The expression of drain current in different region for different metal-insulator gate geometric HEMT is given by .…”

“…This increase in depletion depth can be accounted in terms of additional charges trapped at the surface of the channel, resulting in a lower electric field peak at the drain-sideedge of the gate and hence, higher BV ds . By considering the finite effect of upper gate electrode as shown in Fig.1 on the device characteristics as in Field Plates (FP) between gate-drain spacing (Γ-gate) (which is usually ignored in T-gate geometries with passivation layer), increase in BV ds [23][24][25][26][27][28][29][30] can be seen owing to increase in depletion depth as a combined effect of both the upper gate electrode and the lower gate in T-gate geometry. Inclusion of FP modulates the electric field profile in such a way that three peaks are obtained in various Γ-gate instead of two peaks as in normal gate device due to the effect of different region of gate in Γ-gate geometry as shown in Fig.…”

“…All these parameter variations have been analyzed by performing analytical analysis supported by simulation work [31]. Generalized analytical models for HEMT [30,[32][33][34] have been used to obtain the analytical results for various metal-insulator geometries by considering different values of insulator thickness and permittivity in various regions of the device under consideration. Taking into account, the present lithographic scenario and controlled thermal reflow treatment [11] on multiresist process for fabrication, a gate geometry has been considered, which upon playing with the insulator thickness and dielectric constant of the material forming the gate-dielectric system can give an account of various metal-insulator geometries in which the effect of FP can be made possible either on source side (SFP), or drain side (DFP) or on both source and drain end (BFP).…”

“…But this additional depletion region formed at the surface of the channel due to trapped charges leads to increase in gate-drain capacitance and channel resistance thereby reducing the gain/cut-off frequency (f T ) of the device. Thus, to have desired characteristics without the emergence of these anomalies, the effect of upper part of the gate should be negligible [23][24][25][26][27][28][29][30], thereby showing a trade-off between the emergence of gate-drain capacitance and channel resistance and the increased breakdown voltage. Device optimization is thus required to tailor the field profile to improve the BV ds and f T of the device.…”