Short and long-term safe operating area considerations in LDMOS transistors

Hower, P.L.; Pendharkar, S.

doi:10.1109/relphy.2005.1493145

Cited by 38 publications

(22 citation statements)

References 8 publications

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“…The SOA is a set of I D -V DS boundary limits within which the device must operate to avoid failure. For ease of discussion, it has been suggested to distinguish between the SOA obtained from short-term stressing and the SOA obtained from long-term stressing [131]. For example, failures caused by snapback or latch-up are of electrical nature and typically occur after short-term stressing at high power density of about 1 MW/cm 2 .…”

Section: Safe Operating Area (Soa)mentioning

confidence: 99%

High-Voltage and Power Transistors

El-Kareh¹,

Hutter²

2015

Silicon Analog Components

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This chapter focuses mainly on the drain-extended MOS transistor, DEMOS, for high voltage applications, and on the lateral double-diffused MOS transistor, LDMOS, for high power applications. In both cases, the drain is extended with a lightly-doped region, referred to as the drift region, to sustain the high voltage. The chapter begins with an analysis of the drift region and its optimization, typically by reduced surface-field (RESURF) techniques. The transistor switching performance is then analyzed, followed by a discussion of DEMOS and LDMOS design considerations and characteristics. High-voltage and high-current effects are then described, including quasi-saturation, body current, on-state breakdown, and safe operating area (SOA). The chapter concludes with selected high-voltage device applications. IntroductionThe MOSFETs discussed in Chap. 6 are designed for digital, analog, mixed-signal, and RF applications that operate in the low-to-medium voltage range of about 0.8-6 V. Many analog applications, however, require transistors that can handle voltages above 20 V and currents in the ampere range. Those transistors are referred to as high-voltage and power transistors. This chapter provides a comprehensive analysis of the drain-extended MOS transistor (DEMOS), for high-voltage and low-current applications, and the lateral double-diffused MOS (LDMOS) transistor, LDMOS, for power applications. (The "D" in LDMOS describes the sequential (double) diffusion of boron and arsenic through the same oxide opening, defining a precise channel length (Chap. 9). The "L" means that the current path is parallel to the silicon surface (lateral), as opposed to "V" in VDMOS where the current is nearly vertical to the silicon surface.) Schematic cross sections of both transistors (Table 7.1). The DEMOS is typically processed without added process complexity, whereas the LDMOS requires optimization of the P-body and N-drift regions to achieve high voltages and currents while minimizing the drain-to-source resistance and transistor area.The interest in bipolar, CMOS, and DMOS (BCD) technologies has been driven primarily by the proliferation of portable electronics, automotive electronics, and the need for energy efficiency. These applications cluster around different operating points, with 24 V for portable electronics; 60 V for automotive, solar, and LED backlighting; 85 V for power over Ethernet; 120 V for telecommunication; and 700 V for offline LED lighting, consumer, and industrial applications. As a result, BCD is now the technology of choice to realize power ICs by most integrated device manufacturers (IDM) and foundries [1][2][3][4][5].This chapter focuses mainly on transistors with voltage capabilities in the range of 20-700 V, where the bulk of the product applications lie.

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Section: Safe Operating Area (Soa)mentioning

confidence: 99%

High-Voltage and Power Transistors

El-Kareh¹,

Hutter²

2015

Silicon Analog Components

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“…Currently, high voltage drain extended MOS (DeMOS) transistors are of great importance, as these devices are compatible with standard CMOS technology with some additional process layers and less costs [1][2][3]. These devices differ from traditional MOS devices in that for the asymmetric device structures, they have an extended drain region consisting of a lowly doped n-type (p-type) drift or graded region to withstand high voltage [1][2][3][4][5].…”

Section: Introductionmentioning

confidence: 99%

“…These devices differ from traditional MOS devices in that for the asymmetric device structures, they have an extended drain region consisting of a lowly doped n-type (p-type) drift or graded region to withstand high voltage [1][2][3][4][5]. As the channel current is flowing at the interface and as the gate or the drain is subjected to high voltage, DeMOS devices are prone to hot carrier injection and trapping.…”

Section: Introductionmentioning

confidence: 99%

“…As the channel current is flowing at the interface and as the gate or the drain is subjected to high voltage, DeMOS devices are prone to hot carrier injection and trapping. Consequently, hot carrier degradation limiting the safe operating area (SOA) of DeMOS transistors has become a major issue [1][2][3][4][5][6][7][8]. Until now, however, a few reports about hot carrier degradation in DeMOS transistors are presented.…”

Section: Introductionmentioning

confidence: 99%

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Locating hot carrier degradation in asymmetric nDeMOS transistors by gated diode technique

Wang

Sun

Zhang

et al. 2008

Journal of Non-Crystalline Solids

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“…safety-critical applications in automotive. Therefore a lot of research is done to understand the different reliability effects in integrated power devices, and to improve and optimise the transistors for maximum reliability [16][17][18][19][20][21][22][23][24][25][26][27][28][29][30][31][32]. Most research is for LDMOS transistors, as these devices are much easier to integrate and as such are more common in smart power technologies.…”

Section: Introductionmentioning

confidence: 99%