2020
DOI: 10.1109/led.2020.2976653
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Sharply Increased Current in Asymmetrically Aligned Polycrystalline Polymer Transistors With Sub-Domain-Size Channels

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Cited by 6 publications
(1 citation statement)
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“…Figure 2b,c shows the transfer and output characteristics of the DPPT-TT transistor, indicating its typical p-type behavior. The operating voltage is relatively low compared to that of the previous research, [38,39] due to the electric-double-layer (EDL) capacitive behavior of the chitosan-based protic electrolyte dielectric. [40] The EDL is formed at the interface between the electrolyte and the channel, whereupon gate-to-channel voltages the depletion/accumulation of interfacial protons induce/reduce holes in the p-type DPPT-TT channel, turning on/off the device, as illustrated in Figure S2 (Supporting Information).…”
Section: Resultsmentioning
confidence: 76%
“…Figure 2b,c shows the transfer and output characteristics of the DPPT-TT transistor, indicating its typical p-type behavior. The operating voltage is relatively low compared to that of the previous research, [38,39] due to the electric-double-layer (EDL) capacitive behavior of the chitosan-based protic electrolyte dielectric. [40] The EDL is formed at the interface between the electrolyte and the channel, whereupon gate-to-channel voltages the depletion/accumulation of interfacial protons induce/reduce holes in the p-type DPPT-TT channel, turning on/off the device, as illustrated in Figure S2 (Supporting Information).…”
Section: Resultsmentioning
confidence: 76%