Shallow Clock Tree Pre-Estimation for Designing Clock Tree Synthesizable Verilog RTLs
Nayoung Kwon,
Daejin Park
Abstract:Clock tree synthesis (CTS) is an important process in determining overall chip timing and power consumption. The CTS is also a time-consuming process for checking the clock tree. If the chip design and specification do not match, the CTS result will be wrong. Many users use licensed electronic design automation (EDA) tools like Synopsys, and Cadence to carry out accurate chip verification. However, when using a licensed EDA tool, it is difficult to change the function and confirm the overall process in detail.… Show more
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