SGRT

Lee, Won-Jong; Shin, Youngsam; Lee, Jae-Don; Kim, Jin-Woo; Nah, Jae-Ho; Jung, Seokyoon; Lee, Shihwa; Park, Hyun-Sang; Han, Tack-Don

doi:10.1145/2492045.2492057

Cited by 56 publications

(2 citation statements)

References 21 publications

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“…The SIMD architecture is a hardware unit in which multiple computing units perform a single operation on different sets of data concurrently [32]. They are widely used in various commercial processors [33,34]. Several state-of-the-art NPUs employ the SIMD architecture as their main computation unit [16,19,21,22,24].…”

Section: Accelerating Cnn On Neural Processing Unitmentioning

confidence: 99%

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CONNA: Configurable Matrix Multiplication Engine for Neural Network Acceleration

Park

Chung

2022

Electronics

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Convolutional neural networks (CNNs) have demonstrated promising results in various applications such as computer vision, speech recognition, and natural language processing. One of the key computations in many CNN applications is matrix multiplication, which accounts for a significant portion of computation. Therefore, hardware accelerators to effectively speed up the computation of matrix multiplication have been proposed, and several studies have attempted to design hardware accelerators to perform better matrix multiplications in terms of both speed and power consumption. Typically, accelerators with either a two-dimensional (2D) systolic array structure or a single instruction multiple data (SIMD) architecture are effective only when the input matrix has shapes that are close to or similar to a square. However, several CNN applications require multiplications of non-squared matrices with various shapes and dimensions, and such irregular shapes lead to poor utilization efficiency of the processing elements (PEs). This study proposes a configurable engine for neural network acceleration, called CONNA, whose computation engine can conduct matrix multiplications with highly utilized computing units, regardless of the access patterns, shapes, and dimensions of the input matrices by changing the shape of matrix multiplication conducted in the physical array. To verify the functionality of the CONNA accelerator, we implemented CONNA as an SoC platform that integrates a RISC-V MCU with CONNA on Xilinx VC707 FPGA. SqueezeNet on CONNA achieved an inference performance of 100 frames per second (FPS) with 2.36 mm2 and 83.55 mW in a 65 nm process, improving efficiency by up to 34.1 times better than existing accelerators in terms of FPS, silicon area, and power consumption.

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Section: Accelerating Cnn On Neural Processing Unitmentioning

confidence: 99%

“…Several platforms were compared: CPU (i3-6100U), GPU (Tesla T4), and well-known accelerators such as SIMD and SA-based implementation [21,22,34,43]. The results are summarized in Tables 10 and 11.…”

Section: Comparision With the State-of-the-art Acceleratorsmentioning

confidence: 99%

CONNA: Configurable Matrix Multiplication Engine for Neural Network Acceleration

Park

Chung

2022

Electronics

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Novel hydroxyl‐containing and thermo‐dehydrocyclizable polycondensation polymers for multifunctional materials: Synthesis, properties, application

Lebedeva

Кононова

Kruchinina

et al. 2021

J of Applied Polymer Sci

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Novel poly(amide‐imide)s and poly(amide‐o‐hydroxy‐imide)s were synthesized in the process of low‐temperature polycondensation of diacid chloride of 2‐(4‐carboxyphenyl)‐1,3‐dioxoisoindoline‐5‐carboxylic acid with a single diamine of 5,5′‐methylenebis(2‐aminophenol (DADHyDPhM) or of 4,4′‐methylenebis(benzeneamine) (DADPhМ), and also with a mixture of named diamines (molar ratios of DADHyDPhM to DADPhМ being equal to 7:3, 1:1, and 3:7). The influence of hydroxy‐imide modifying units (fragments) introduced into the basic poly(amide‐imide) on its thermal stability (the processes of polymers destruction proceed intensively in the temperature range from 400 to 600°C and has a complex character); parameters of pervaporation through heat‐resistant films prepared from polymer solutions were analyzed. Polymer films are rigid materials (modulus of elasticity–3 to 4 GPa) with a strength above 100 MPa. Heating up to 300°C leads for all three compositions to a noticeable increase in the elastic modulus and to a pronounced tendency to increase the strength characteristics.

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Fast filter bank convolution for three-dimensional wavelet transform by shared memory on mobile GPU computing

Zhao

2015

J Supercomput

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Mobile GPU applications usually constrain by the real-time requirement. However, FLOPS of mobile GPU is limited by the size and power supply of the SoC systems. Same to desktop GPUs, the mobile GPU consists of an on-chip memory hierarchy, and proper usage of memory hierarchy accelerates mobile GPU applications such as Discrete Wavelet Transform (DWT) to satisfy the real-time requirement. In this paper, by taking advantage of GPU shared memory in Tegra K1, a mobile GPU from Nvidia, we develop Bank Conflict Free Shared Memory Parallel DWT for mobile GPU applications. Computational results show that, with the display resolution of 640 × 350 (EGA), Bank Conflict Free Shared Memory Parallel DWT is significantly faster than SoC CPU-based DWT. Computational results also show that, with the display resolution of 320 × 200 (CGA), 640 × 480 (VGA), 800 × 600 (SVGA) and 1024 × 768 (XGA), Bank Conflict Free Shared Memory Parallel DWT can generally satisfy the real-time requirement.

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SGRT

Cited by 56 publications

References 21 publications

CONNA: Configurable Matrix Multiplication Engine for Neural Network Acceleration

CONNA: Configurable Matrix Multiplication Engine for Neural Network Acceleration

Novel hydroxyl‐containing and thermo‐dehydrocyclizable polycondensation polymers for multifunctional materials: Synthesis, properties, application

Fast filter bank convolution for three-dimensional wavelet transform by shared memory on mobile GPU computing

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