SFQ Parallel Encoders Promising for Video Imaging With Superconductor Stripline Detectors

Tanaka, Masamitsu; Kozaka, Misaki; Kamiya, Kyohei; Usenmez, Kubra; Aydogan, Eren Can; Razmkhah, Sasan

doi:10.1109/tasc.2020.3013385

Cited by 4 publications

(1 citation statement)

References 18 publications

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“…Superconductor Josephson logic families, such as rapid single-flux-quantum (RSFQ) logic [1] and its energyefficient variants [2,3], can operate with much smaller energy dissipation than that of conventional semiconductor circuits and are thus promising technology for applications requiring high energy efficiency: low-power microprocessors [4][5][6], readout circuits for superconducting detectors [7][8][9][10], and interface circuits for superconducting qubits [11,12]. Among various Josephson logic families, adiabatic quantum-flux-parametron (AQFP) logic [13,14] exhibits extremely high energy-efficiency.…”

Section: Introductionmentioning

confidence: 99%

Low-Latency Adiabatic Quantum-Flux-Parametron Circuit Integrated With a Hybrid Serializer/Deserializer

et al. 2022

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Adiabatic quantum-flux-parametron (AQFP) logic is an ultra-low-power superconductor logic family. AQFP logic gates are powered and clocked by dedicated clocking schemes using ac excitation currents to implement an energy-efficient switching process, adiabatic switching. We have proposed a lowlatency clocking scheme, delay-line clocking, and demonstrated basic AQFP logic gates. In order to test more complex circuits, a serializer/deserializer (SerDes) should be incorporated into the AQFP circuit under test, since the number of input/output (I/O) cables is limited by equipment. Therefore, in the present study we propose and develop a novel SerDes for testing delay-line-clocked AQFP circuits by combining AQFP and rapid single-flux-quantum (RSFQ) logic families, which we refer to as the AQFP/RSFQ hybrid SerDes. The hybrid SerDes comprises RSFQ shift registers to facilitate the data storage during serial-toparallel and parallel-to-serial conversion. Furthermore, all the component circuits in the hybrid SerDes are clocked by the identical excitation current to synchronize the AQFP and RSFQ parts. We fabricate and demonstrate a delay-line-clocked AQFP circuit (8-to-3 encoder, which is the largest delay-line-clocked circuit ever designed) integrated with the hybrid SerDes at 4.2 K up to 4.5 GHz. Our measurement results indicate that the hybrid SerDes enables the testing of delay-line-clocked AQFP circuits with only a few I/O cables and is thus a powerful tool for the development of very large-scale integration AQFP circuits.

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