SEU tolerant memory design for the ATLAS pixel readout chip

Menouni, M.; Arutinov, D.; Backhaus, M.; Barbero, M.; Beccherle, R.; Breugnon, P.; Caminada, L.; Dubé, S.; Darbo, G.; Fleury, J.; Fougeron, D.; Garcia-Sciveres, M.; Gensolen, F.; Gnani, D.; Gromov, V.; Hemperek, T.; Jensen, F.; Kluit, R.; Krueger, Hans; Kruth, A.; Lu, Y.; Mekkaoui, A.; Rozanov, A.; Schipper, J.; Zivkovic, V.

doi:10.1088/1748-0221/8/02/c02026

Cited by 6 publications

(11 citation statements)

References 4 publications

(4 reference statements)

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“…The IBL data output is a serial Low Voltage Differential Signal (LVDS), 8b/10b encoded at a rate of 160 MBit/s. The chip has many configurable settings that are stored in triple-redundant registers providing the required radiation hardness to single event upsets (SEU) [35].…”

Section: The Fe-i4 Front-end Chipmentioning

confidence: 99%

“…An FPGA running a MicroBlaze processor on each of the ROD and BOC cards handles the Ethernet connection between them. The BOC card is interfaced to the detector and to the ATLAS read-out system: the detector interface uses commercial SNAP12 optical transmitters and receivers 34 ; the read-out interface is via S-LINK connections 35 .…”

Section: Off-detector Read-out Electronics (Rod/boc)mentioning

confidence: 99%

“…As shown in Figure 50, data communication between the detector and the ROD/BOC cards is bi-directional: one control and two parallel data processing paths link the ROD/BOC pair to an IBL half-stave. The BOC card is interfaced to the detector and to the ATLAS read-out system: the detector interface uses commercial SNAP12 optical transmitters and receivers 34 ; the read-out interface is via S-LINK connections 35 .…”

Section: Off-detector Read-out Electronics (Rod/boc)mentioning

confidence: 99%

“…These histograms are transmitted using the Ethernet protocol 34 The SNAP12 Multi-Source Agreement (May 2002) outlines specifications for the mechanical, electrical and optical interfaces of 12-channel pluggable parallel optical transmitter and receiver modules. 35 S-LINK, for simple link interface, is a high-performance data acquisition standard developed at CERN. 36 Unless otherwise specified, all FPGAs are from the XiLinx Spartan-6 family.…”

Section: Off-detector Read-out Electronics (Rod/boc)mentioning

confidence: 99%

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Production and integration of the ATLAS Insertable B-Layer

et al. 2018

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The ATLAS IBL CollaborationDuring the shutdown of the CERN Large Hadron Collider in 2013-2014, an additional pixel layer was installed between the existing Pixel detector of the ATLAS experiment and a new, smaller radius beam pipe. The motivation for this new pixel layer, the Insertable B-Layer (IBL), was to maintain or improve the robustness and performance of the ATLAS tracking system, given the higher instantaneous and integrated luminosities realised following the shutdown. Because of the extreme radiation and collision rate environment, several new radiation-tolerant sensor and electronic technologies were utilised for this layer. This paper reports on the IBL construction and integration prior to its operation in the ATLAS detector.The ATLAS [1] general purpose detector is used for the study of proton-proton (pp) and heavy-ion collisions at the CERN Large Hadron Collider (LHC) [2]. It successfully collected data at pp collision energies of 7 and 8 TeV in the period of 2010-2012, known as Run 1. Following an LHC shutdown in 2013-2014 (LS1), it has collected data since 2015 at a pp collision energy of 13 TeV (the so-called Run 2).The ATLAS inner tracking detector (ID) [1, 3] provides charged particle tracking with high efficiency in the pseudorapidity 1 range of |η| < 2.5. With increasing radial distance from the interaction region, it consists of silicon pixel and micro-strip detectors, followed by a transition radiation tracker (TRT) detector, all surrounded by a superconducting solenoid providing a 2 T magnetic field.The original ATLAS pixel detector [4,5], referred to in this paper as the Pixel detector, was the innermost part of the ID during Run 1. It consists of three barrel layers (named the B-Layer, Layer 1 and Layer 2 with increasing radius) and three disks on each side of the interaction region, to guarantee at least three space points over the full tracking |η| range. It was designed to operate for the Phase-I period of the LHC, that is with a peak luminosity of 1 × 10 34 cm −2 s −1 and an integrated luminosity of approximately 340 fb −1 corresponding to a TID of up to 50 MRad 2 and a fluence of up to 1 × 10 15 n eq /cm 2 NIEL. However, for luminosities exceeding 2 × 10 34 cm −2 s −1 , which are now expected during the Phase-I operation, the read-out efficiency of the Pixel layers will deteriorate. This paper describes the construction and surface integration of an additional pixel layer, the Insertable B-Layer (IBL) [6], installed during the LS1 shutdown between the B-Layer and a new smaller radius beam pipe. The main motivations of the IBL were to maintain the full ID tracking performance and robustness during Phase-I operation, despite read-out bandwidth limitations of the Pixel layers (in particular the B-Layer) at the expected Phase-I peak luminosity, and accumulated radiation damage to the silicon sensors and front-end electronics. The IBL is designed to operate until the end of Phase-I, when a full tracker upgrade is planned [7] for high luminosity LHC (HL-LHC) operation from approximately ...

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Section: The Fe-i4 Front-end Chipmentioning

confidence: 99%

Section: Off-detector Read-out Electronics (Rod/boc)mentioning

confidence: 99%

Section: Off-detector Read-out Electronics (Rod/boc)mentioning

confidence: 99%

Section: Off-detector Read-out Electronics (Rod/boc)mentioning

confidence: 99%

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Production and integration of the ATLAS Insertable B-Layer

et al. 2018

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“…Such interactions are di cult to model, but an understanding of SEU rates is essential for detector operations. This Section presents an in-situ measurement of the probability of bit flips in the radiation hard memory cells known as Dual Interlocked CElls, or DICE latches [171] [172], which store the configuration of each pixel in the IBL.…”

Section: C1 Single Event Upsetmentioning

confidence: 99%