SEU-Susceptibility of Logical Constants in Xilinx FPGA Designs

Quinn, Heather; Allen, Gregory R.; Swift, G.M.; Tseng, Chen Wei; Graham, Paul; Morgan, Keith S.; Ostler, Patrick

doi:10.1109/tns.2009.2033925

Cited by 9 publications

(2 citation statements)

References 8 publications

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“…In [Quinn et al 2007b], first results for Virtex-5 are published. In 2009, results regarding the SEUsusceptibility of logical constants were presented [Quinn et al 2009a]. In the same year, a paper describing their methodology for static and dynamic testing was published too [Quinn et al 2009b].…”

Section: Accelerated Radiation Testingmentioning

confidence: 99%

Mitigation of Radiation Effects in SRAM-Based FPGAs for Space Applications

Siegle

Vladimirova

Ilstad³

et al. 2015

ACM Comput. Surv.

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The use of static random access memory (SRAM)-based field programmable gate arrays (FPGAs) in harsh radiation environments has grown in recent years. These types of programmable devices require special mitigation techniques targeting the configuration memory, the user logic, and the embedded RAM blocks. This article provides a comprehensive survey of the literature published in this rich research field during the past 10 years. Furthermore, it can also serve as a tutorial for space engineers, scientists, and decision makers who need an introduction to this topic.

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Section: Accelerated Radiation Testingmentioning

confidence: 99%

Mitigation of Radiation Effects in SRAM-Based FPGAs for Space Applications

Siegle

Vladimirova

Ilstad³

et al. 2015

ACM Comput. Surv.

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“…We focus on the NBTI degradations of the routing switch shown in Fig. 3, which is commonly used in FPGAs [13], [14]. There are two inverters (INV0 and INV1), an NMOS transistor to be used for a switch, a pull-up PMOS transistor and a configuration bit determining ON/OFF of the switch.…”

Section: Setup For Fpga Aging Simulationsmentioning

confidence: 99%

NBTI-Induced Delay Degradation Analysis of FPGA Routing Structures

Yabuuchi

Kobayashi

2012

IPSJ Transactions on System LSI Design Methodology

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Abstract:Reliability issues, such as soft errors, process variations and Negative Bias Temperature Instability (NBTI), become dominant on Field Programmable Gate Arrays (FPGAs) fabricated in a nanometer process. We focus on aging degradation by NBTI, which causes threshold voltage shifts on PMOS transistors. We characterize delay degradation in the routing structures on FPGAs. The rising and falling delays vary due to NBTI and heavily depend on circuit configurations. In the independent routing switch, the delay fluctuation due to NBTI can be minimized by transistor sizing. The falling delay does not change after 10-years degradation. In the routing structures composed of the routing switches and wires, the delay fluctuation depends on the wire length and can be minimized to optimize the wire length. We also show that the signal flipping can reduce the delay degradation from 11.3% to 2.76% on the routing resources.

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