SEU Simulation Framework for Xilinx FPGA: First Step towards Testing Fault Tolerant Systems

Straka, Martin; Kastil, Jan; Kotásek, Zdenĕk

doi:10.1109/dsd.2011.32

Cited by 47 publications

(24 citation statements)

References 14 publications

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“…The MPSoC contains 4 Microblaze processor systems which implement a fault tolerant architecture for a small satellite avionics platform. Assessing the performance of digital designs under radiation can be performed through circuit simulations of the critical charges and nodes, software simulations and fault injections in hardware [17][18][19][20][21] . We chose to implement our system using hardware fault injection.…”

Section: The Emulation Results and Discussionmentioning

confidence: 99%

LEO Single Event Upset Emulator for Validation of FPGA Based Avionics Systems

Ibrahim

Asami

Cho

2014

AEROSPACE TECHNOLOGY JAPAN

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This paper presents a complete design and implementation of a Single Event Upset (SEU) emulation system that can be used to inject faults Static Random Access Memory (SRAM) based Field Programmable Gate Array (FPGA). The FPGA is used to implement an avionics system for a small satellite. The fault injector emulates the expected Single Event Upset (SEU) rate as it would be in the Low Earth Orbit (LEO) of the polar orbiting satellites at inclinations close to 98° deg., and altitude of about 670 km. The emulator injects faults in the configuration bit-stream of the FPGA without stopping its operation. It makes use of the partial reconfiguration feature of today's FPGAs. This provides a facility to assess the design performance in space even if radiation testing will not be conducted before launching. Also, it simulates the expected upset rate and hence calculates the corresponding data failure rates for Triple Modular Redundancy (TMR) fault tolerant designs. The system was implemented using the Xilinx Virtex-LX50T FPGA. The FPGA suffered system failures during the fault injection test. It recovered about 50% of the failures. TMR simulation at an upset rate of 0.1 upsets (per bit per second) for a data size of 2048 bits showed that about 33% of the faults will be fully corrected.

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Section: The Emulation Results and Discussionmentioning

confidence: 99%

LEO Single Event Upset Emulator for Validation of FPGA Based Avionics Systems

Ibrahim

Asami

Cho

2014

AEROSPACE TECHNOLOGY JAPAN

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“…Второй способ позволяет избежать дорогостоящего изготов-ления экспериментальных образцов в циклах т е с т и р ов а н и я-пер е п р о е к т и р ов а н и я и поэ -тому используется многими разработчиками. Известно множество реа лизаций аппаратно-программных решений (в частности, [2][3][4][5]) для контроля работоспособности СнК в условиях воздействия космической радиации. Имеются решения на основе ПЛИС-прототипирования, которые обеспечивают оптима льное соотно-шение цены и быстродействия ПАК [6].…”

Section: #8 / 70 / 2016unclassified

“…The second method avoids the costly fabrication of experimental samples in the cycles of testing, redesign, and therefore is used by many developers. Many implementations of hardware and software solutions to control the operability of the SoC under conditions of exposure to cosmic radiation are well known (in particular, [2][3][4][5]). There are solutions based on FPGA prototyping, which provide the optimal ratio of price and performance of HSS [6].…”

Section: #8 / 70 / 2016mentioning

confidence: 99%

Implementation of experimental software prototype for control of fault tolerance of IC design

Brekhov¹,

Klimenko²,

Shdanov³

et al. 2016

NanoRus

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Представлена совокупность разработанных модулей, образующих ядро программного обеспечения экспериментального образца программно-аппаратного комплекса (ПАК) контроля сбоеустойчивости проекта микросхемы. Контроль сбоеустойчивости основан на использовании расширенного метода внесения неисправностей, подразумевающего моделирование многоуровневого воздействия неисправностей. Программные модули ПАК обеспечивают обработку проекта микросхемы, генерацию списка сбоев, генерацию тестовых воздействий и обработку результатов моделирования. Технические решения, воплощенные в ПАК, позволяют выполнять гибкий выбор источников возникновения сбоев в микросхеме и получать детальную информацию о локализации критических сбоев, приводящих к отказу моделируемой системы. Использование ПЛИС-прототипирования вместо программных симуляторов при моделировании позволяет добиться ускорения процесса контроля сбоеустойчивости. A set of developed modules that form the software core of the experimental prototype of a hardware-software system (HSS) for control of fault tolerance of IC design is presented. Control of fault tolerance is based on the use of the extended method of fault injection, which implies the modeling of the multi-level impact of faults. Software modules of HSS provides processing of the IC design, generation of the list of faults, generation of test inputs and processing of the simulation results. Technical solutions embodied in the HSS, allow a flexible choice of sources of faults in the chip and obtaining detailed information about the localization of the critical faults that caused a failure of the simulated system. The use of FPGA prototyping instead of software simulation allows to accelerate the control of fault tolerance. Р азработка устройств типа "система на кри-сталле" (СнК) включает в себя решение целого комплекса взаимосвязанных задач от про-ектирования структуры и выбора аппаратной базы до реализации экспериментальных образ-цов. При этом, проведение тестирования рабо-тоспособности на этапе разработки имеет пер-востепенное, а для устройств на основе заказ-ных и полузаказных микросхем -критическое значение, так как качество тестирования суще-с т в енно в ли яе т на с тои мо с т ь ра зраб о ток. К устройствам специального назначения (в част-ности, компонентам космической техник и) предъявляются дополнительные требования по обеспечению работоспособности в условиях воздействия агрессивных внешних сред. В связи с этим, актуально тестирование сбоеустойчиво-сти устройств типа СнК на этапе их разработки. Военные и космические технологии *Московский авиационный институт (национальный исследовательский университет) / Moscow Aviation Institute (National Research University).

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“…Several injection boards have been developed in order to evaluate the impact of SEUs in the configuration memory of circuits mapped on SRAM-based FPGAs [5,8,178,191]. These boards emulate the occurrence of SEUs by modifying the bitstream of the target system whose dynamic behavior is then evaluated.…”

Section: Fault Injectionmentioning

confidence: 99%

Analysis and test of the effects of single event upsets affecting the configuration memory of SRAM-based FPGAs

Cassano

2014

2014 International Test Conference

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SommarioI dispositivi FPGA con memoria di configurazione SRAM sono sempre più rilevanti in un grande numero di campi applicativi, dal contesto automobilistico a quello aerospaziale. Questi campi applicativi sono caratterizzati dalla presenza di radiazioni capaci di causare Single Event Upsets (SEUs) in dispositivi digitali. Tali guasti hanno effetti particolarmente dannosi sui sistemi implementati in tecnologia SRAM-based FPGA, in quanto sono in grado non solo di danneggiare temporaneamente il comportamento del sistema, cambiando il contenuto di flip-flop e memorie, ma anche di cambiare permanentemente la funzionalità implementata dal sistema stesso, cambiando il contenuto della memoria di configurazione. Il design di applicazioni safetycritical richiede l'utilizzo, prima possibile durante il flusso di progetto del sistema, di metodologie accurate per la valutazione della sensitività ai SEU del sistema stesso. Inoltre è necessario essere in grado di rilevare l'occorrenza di SEU durante il funzionamento del sistema. A questo scopo è necessario generare test patterns durante il progetto del sistema ed è poi necessario applicare tali test patterns agli input del sistema durante il suo funzionamento.In questa tesi descriviamo il progetto e l'implementazione di strumenti software utili al progettista di applicazioni safety-critical basati su tecnologia SRAM-based FP-GA per la valutazione della sensitività ai SEU del sistema e per la generazione di test pattern utili al rilevamento di SEU nella memoria di configurazione durante la vita del sistema. La caratteristica principale di questi strumenti è l'implementazione di un modello di SEU nei bit di configurazione che controllano le risorse logiche e di routing di un dispositivo FPGA che risulta essere molto più accurato rispetto ai classici modelli stuck-at ed open/short che sono in genere considerati nell'analisi di circuiti digitali. In tal modo gli strumenti proposti risultano essere molto più accurati rispetto a strumenti simili, sia accademici che commerciali, attualmente disponibili per l'analisi dei guasti in dispositivi digitali ma non specificamente sviluppati per dispositivi FPGA.In particolare tre strumenti sono stati progettati ed implementati: (i) ASSESS: Accurate Simulator of SEuS affecting the configuration memory of SRAM-based FPGAs, un simulatore di SEU nella memoria di configurazione di sistemi implementati in tecnologia SRAM-based FPGA, finalizzato a valutare la sensitività del sistema ai SEU prima possibile nel processo di sviluppo del sistema; (ii) UA 2 TPG: Untestability Analyzer and Automatic Test Pattern Generator for SEUs Affecting the Configuration Memory of SRAM-based FPGAs, uno strumento di analisi statica per l'identificazione dei SEU non testabili e per la generazione automatica di test patterns per il rilevamento del 100% dei SEU testabili; e (iii) GABES: Genetic Algorithm Based Environment for SEU Testing in SRAM-FPGAs, un ambiente basato su un algoritmo genetico per la generazione ed ottimizzazione di test patterns per il rilevamento di...

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SEU Simulation Framework for Xilinx FPGA: First Step towards Testing Fault Tolerant Systems

Cited by 47 publications

References 14 publications

LEO Single Event Upset Emulator for Validation of FPGA Based Avionics Systems

LEO Single Event Upset Emulator for Validation of FPGA Based Avionics Systems

Implementation of experimental software prototype for control of fault tolerance of IC design

Analysis and test of the effects of single event upsets affecting the configuration memory of SRAM-based FPGAs

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