SEU simulation and testing of resistor-hardened D-latches in the SA3300 microprocessor

Sexton, F.W.; Corbett, Wayne T.; Treece, R.K.; Hass, K.J.; Hughes, K.L.; Axness, Carl L.; Hash, G.L.; Shaneyfelt, M.R.; Wunsch, T.F.

doi:10.1109/23.124141

Cited by 29 publications

(9 citation statements)

References 13 publications

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“…Meanwhile, soft errors have been a concern for many years for ICs operating in space environments. To improve soft error immunity, manufacturers of radiation-hardened ICs may use feedback elements (e.g., resistors, capacitors) to slow the propagation of voltage transients, at the expense of performance [5]. Other techniques to decrease soft error sensitivity include circuit design techniques that lead to increased transistor counts and layout area [6], [7].…”

Section: Introductionmentioning

confidence: 99%

SEU-sensitive volumes in bulk and SOI SRAMs from first-principles calculations and experiments

Dodd

Shaneyfelt

Horn

et al. 2001

IEEE Trans. Nucl. Sci.

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176

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Large-scale three-dimensional (3-D) device simulations, focused ion microscopy, and broadbeam heavy-ion experiments are used to determine and compare the SEU-sensitive volumes of bulk-Si and SOI CMOS SRAMs. Single-event upset maps and cross-section curves calculated directly from 3-D simulations show excellent agreement with broadbeam cross section curves and microbeam charge collection and upset images for 16 K bulk-Si SRAMs. Charge-collection and single-event upset (SEU) experiments on 64 K and 1 M SOI SRAMs indicate that drain strikes can cause single-event upsets in SOI ICs. 3-D simulations do not predict this result, which appears to be due to anomalous charge collection from the substrate through the buried oxide. This substrate charge-collection mechanism can considerably increase the SEU-sensitive volume of SOI SRAMs, and must be included in single-event models if they are to provide accurate predictions of SOI device response in radiation environments.

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Section: Introductionmentioning

confidence: 99%

SEU-sensitive volumes in bulk and SOI SRAMs from first-principles calculations and experiments

Dodd

Shaneyfelt

Horn

et al. 2001

IEEE Trans. Nucl. Sci.

Self Cite

176

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show abstract

“…The circuit calculation should lead to the critical charge of the median cell if nominal circuit parameters are used. Several examples exist in the literature where a careful calculation has been performed, but when the results are compared with a charge derived from the measured onset threshold, it is necessary to assume an unexpected charge collection depth or an unexpected charge multiplication factor to reconcile the calculations with the experiment [45,46,47,48,49,50]. These authors all discuss their expected charge collection depths based on the technology.…”

Section: Importance Of a Distribution Of Sensitivitiesmentioning

confidence: 98%

“…The present data presentation and interpretation do not require that correction. Figure 12 shows data obtained by Sexton for hardened and unhardened devices, at several temperatures [50]. The published data has has been corrected by Sexton for the energy loss in 3.7 micrometers of overlayer.…”

Section: Application To Seu Hard Devicesmentioning

confidence: 99%

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Rate prediction for single event effects-a critique

Petersen

Pickel

Adams

et al. 1992

IEEE Trans. Nucl. Sci.

244

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“…When the necessary resistance exceeds 100 kΩ it becomes difficult to manufacture polysilicon resistors that are both small and consistent in value. Furthermore, these lightly doped resistors have a large negative temperature coefficient [89,90].…”

Section: Seu-resistant Latch Circuitsmentioning

confidence: 99%

Magnetic Random Access Memory for Embedded Computing

Donohoe¹

2007

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Public reporting burden for this collection of information is estimated to average 1 hour per response, including the time for reviewing instructions, searching existing data sources, gathering and maintaining the data needed, and completing and reviewing this collection of information. MRAM_II_2007-Final SPONSORING / MONITORING AGENCY NAME(S) AND ADDRESS(ES) 10. SPONSOR/MONITOR'S ACRONYM(S)Air Force Research Laboratory AFRL/RVSE Space Vehicles Directorate 3550 Aberdeen Ave. SE SPONSOR/MONITOR'S REPORTKirtland AFB, NM 87117-5776 NUMBER(S) AFRL-RV-PS-TR-2007-1196 DISTRIBUTION / AVAILABILITY STATEMENTApproved for public release; distribution is unlimited. (Clearance #VS07-0688) SUPPLEMENTARY NOTESThis report is published in the interest of scientific and technical information exchange. The established procedures for editing reports were not followed for this technical report. ABSTRACTThe goal of this research was to develop an embedded magnetic memory technology to be integrated into Complementary Metal Oxide Semiconductor (CMOS) integrated circuit fabrication process to provide radiation-hard, logic elements and small random-access memories. The goal is not to provide largescale, bulk memory, but latches and flip flops that serve as state and data registers for sequential logic, and configuration registers for configurable logic. The benefits to spacecraft systems include the ability to power-down a subsystem while retaining system state, thus saving energy until the subsystem is required. The subsystem can then be powered-up and begin operating in milliseconds. The technology is based on a unique, PacMan-shaped magnetic tunneling junction (MTJ) cell developed at the University of Idaho. The focus of this research is to refine the PacMan cell to make it practical for integration into CMOS circuits, to develop CMOS circuits that employ the magnetic cells, and to integrate the cells onto a CMOS process. The process produced two circuit designs based on magnetic memory elements: a magnetic latch, and a magnetic shadow memory to serve as a backup to volatile electronic memory. ii University of Idaho report MRAM_II_2007-Final SUBJECT TERMS CMOS, MTJ Cell

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SEU simulation and testing of resistor-hardened D-latches in the SA3300 microprocessor

Cited by 29 publications

References 13 publications

SEU-sensitive volumes in bulk and SOI SRAMs from first-principles calculations and experiments

SEU-sensitive volumes in bulk and SOI SRAMs from first-principles calculations and experiments

Rate prediction for single event effects-a critique

Magnetic Random Access Memory for Embedded Computing

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