SEU mitigation of rad-tolerant Xilinx FPGA using external scrubbing for geostationary mission

Kumar, Mahesh; Digdarsini, Durga; Misra, Neeraj Kumar; Ram, T. V. S.

doi:10.1109/indicon.2016.7838971

Cited by 7 publications

(7 citation statements)

References 3 publications

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“…The soft-error interval can be estimated as 2.00 hr under a radiation environment of 0.1 high-energy charged particles/s. In this case, by not using a partial reconfiguration, the soft-error tolerance is insufficient as in conventional studies [9], [10]. Here, all reconfiguration patterns have been confirmed.…”

Section: Experiments System and Resultssupporting

confidence: 46%

“…Under space radiation environments, soft-errors occur frequently on the configuration memory of FPGAs [6], [7], [8], as do dynamic random access memories (DRAMs) and static random access memories (SRAMs) [4], [5]. To decrease the frequency of soft-errors of the configuration memory, various scrubbing methods have been proposed that can refresh the configuration memory on an FPGA with a single configuration context [9], [10], [11], [12], [13].…”

Section: Introductionmentioning

confidence: 99%

“…Blind scrubbing methods present benefits in terms of simple architecture and simple control. However, the mean time to repair (MTTR) for blind scrubbing methods is too long a period or over 100 ms, such that the softerror tolerance of such blind scrubbing methods is not good [9], [10].…”

Section: Introductionmentioning

confidence: 99%

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Sequential Circuit Implementation Method for Multi-Context Scrubbing Operations on FPGAs

Murakami

Watanabe

2021

2021 IEEE International Symposium on Circuits and Systems (ISCAS)

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This paper presents a proposal for a sequential circuit implementation method for multi-context scrubbing operations that can treat soft-error and permanent failure issues simultaneously. Although multi-context scrubbing operations can treat permanent failure issues on field programmable gate arrays (FPGAs), implementing sequential circuits is difficult because the flip-flop location must be changed while maintaining sequential operations. Therefore, no multi-context scrubbing operation including a sequential circuit has been demonstrated to date. As described herein, a multi-context scrubbing operation using a simple 8-bit counter circuit has been demonstrated perfectly on an Artix-7 FPGA (XC7A35TICSG324-1L). This paper presents experimentally obtained results of that demonstration.

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Section: Experiments System and Resultssupporting

confidence: 46%

Section: Introductionmentioning

confidence: 99%

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Sequential Circuit Implementation Method for Multi-Context Scrubbing Operations on FPGAs

Murakami

Watanabe

2021

2021 IEEE International Symposium on Circuits and Systems (ISCAS)

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“…The aim is to detect and correct, avoiding a complete failure of the device operations. An external memory scrubber using a rad-hard FPGA to check the configuration memory of the SRAM payload FPGA is described in [10]. Considering the importance of this mechanism to detect and be able to correct radiation-induced errors, Xilinx provides a hardware IP core to rapidly and seamlessly include this mitigation technique in a design [11].…”

Section: Introductionmentioning

confidence: 99%

Fault-Tolerant FPGA-Based Nanosatellite Balancing High-Performance and Safety for Cryptography Application

et al. 2021

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With the growth of the nano-satellites market, the usage of commercial off-the-shelf FPGAs for payload applications is also increasing. Due to the fact that these commercial devices are not radiation-tolerant, it is necessary to enhance them with fault mitigation mechanisms against Single Event Upsets (SEU). Several mechanisms such as memory scrubbing, triple modular redundancy (TMR) and Dynamic and Partial Reconfiguration (DPR), can help to detect, isolate and recover from SEU faults. In this paper, we introduce a dynamically reconfigurable platform equipped with configuration memory scrubbing and TMR mechanisms. We study their impacts when combined with DPR, providing three different execution modes: low-power, safe and high-performance mode. The fault detection mechanism permits the system to measure the radiation level and to estimate the risk of future faults. This enables the possibility of dynamically selecting the appropriate execution mode in order to adopt the best trade-off between performance and reliability. The relevance of the platform is demonstrated in a nano-satellite cryptographic application running on a Zynq UltraScale+ MPSoC device. A fault injection campaign has been performed to evaluate the impact of faulty configuration bits and to assess the efficiency of the proposed mitigation and the overall system reliability.

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“…If the number of the errors in the memory units exceeds the fault tolerant limit, the errors can not be corrected. Scrubbing technologies [35] are used to mitigate the cumulative errors. It uses free clocks periods to read back the data from the memory to operate the correction.…”

Section: Introductionmentioning

confidence: 99%

A self-scrubbing scheme for embedded systems in radiation environments

Zhai

Saha

et al. 2020

2020 IEEE 26th International Symposium on on-Line Testing and Robust System Design (IOLTS)

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SRAMs are very sensitive to radiation effects. When embedded systems working in the extreme radiation environments, bit flips may occur frequently and decrease the reliability of the systems significantly. In this paper, a self-scrubbing scheme is proposed for embedded systems in extreme radiation environments. In the proposed scheme, both scrubbing and error correcting codes are used to mitigate a large number of the errors in the RAMs. Along with this, a separate scrubber is designed to scrub the RAM independently, when the CPUs are busy. In addition, the scrubber is a portable module and the hardware cost does not grow with the size of the available RAM. The results of the experiments show that, in the neutron radiation environments where the error rate in the unhardened RAMs is approximately 1.2bit/(KB•h), while the error rate of the self-scrubbing RAMs is less than 8.7 × 10 −5 bit/(KB•h), which is one fifth of the error rate of the conventional ECC RAMs.

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SEU mitigation of rad-tolerant Xilinx FPGA using external scrubbing for geostationary mission

Cited by 7 publications

References 3 publications

Sequential Circuit Implementation Method for Multi-Context Scrubbing Operations on FPGAs

Sequential Circuit Implementation Method for Multi-Context Scrubbing Operations on FPGAs

Fault-Tolerant FPGA-Based Nanosatellite Balancing High-Performance and Safety for Cryptography Application

A self-scrubbing scheme for embedded systems in radiation environments

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