Settling time optimization in three-stage amplifiers with reversed nested Miller compensation

Abstract

This paper presents a new time-domain design procedure for three-stage amplifiers with reversed nested Miller compensation (RNMC). By utilizing this method, the values of the compensation capacitors are properly selected to achieve the best settling time. To demonstrate the effectiveness of the proposed method, a three-stage amplifier is designed and simulated in a 1V, 90nm CMOS technology. Simulation results show that by using this method, the settling time of the threestage amplifier is approximately halved in comparison with the conventional approaches.

Performance improvement of fractional N-PLL synthesizers for digital communication applications

“…The settling time is proportional to the loop filter's bandwidth, which should be ten times less than the reference frequency to keep the loop stable. The faster the settling process, the wider the loop bandwidth [16]- [19]. Therefor to achieve a faster transient settling time, a PLL-based frequency synthesizer needs a high reference frequency.…”

Robust design of CMOS amplifiers oriented to settling‐time specification

“…In recent years, the design of CMOS amplifiers from settling-time specifications has gained more and more attention because of the growing interest in high-performance discrete-time circuits such as precision switched-capacitor (SC) circuits, and analog-to-digital converters [18][19][20][21][22][23][24][25][26]. In the literature, the analysis has been mainly devoted to two-stage [25,26] and three-stage [18][19][20][21][22][23][24] OTAs, and different design approaches have been presented. Pole-zero cancellation and tuning of phase margin (PM) or damping factor ( ) have been suggested to improve the settling time of multistage amplifiers [18,19].…”

“…Pole-zero cancellation and tuning of phase margin (PM) or damping factor ( ) have been suggested to improve the settling time of multistage amplifiers [18,19]. Conversely, other works have exploited the closed-loop transfer function and/or numerical simulations to optimize the settling-time performance [20][21][22][23][24][25][26]. However, many of these papers provide complex relationships between the settling time and the amplifier parameters, which reduce their effective usage in a real design.…”