SET logic driving capability and its enhancement in 3-D integrated SET–CMOS circuit

Parekh, Rutu; Beauvais, J.; Drouin, Dominique

doi:10.1016/j.mejo.2014.05.020

Cited by 16 publications

(8 citation statements)

References 12 publications

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“…The SET-based computing system design has been implemented using Verilog-A model [29]. The model file provides flexibility to set values of [28]. The interconnect capacitance is computed based on the SET fabrication parameters for the BEOL fabrication process.…”

Section: Set Design Parameters and Interconnect Parasitic Extractionmentioning

confidence: 99%

“…3, the device's physical parameters for gate capacitance are

W_{g}

t_{g}

, and

d_{g}

whereas for tunnel junction, they are

W_{i}

t_{i}

, and

d_{i}

. The proposed SET has physical parameters

W_{g} = 30 nm

t_{g} = 1 - 10 nm

d_{g} = 20 - 60 nm

W_{i} = 3 - 20 nm

t_{i} = 1 - 10 nm

, and

d_{i} = 2 - 8 nm

, which are considered from [9, 28]. By selecting the appropriate SET physical dimensions it is possible to obtain the desired SET capacitance values.…”

Section: Set‐based Computing System Designmentioning

confidence: 99%

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Design of prominent SET‐based high performance computing system

Patel

Agrawal

Parekh

2020

IET Circuits, Devices & Systems

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Over the past several decades, the performance of existing complementary metal oxide semiconductor (CMOS) technology has been improved by scaling of the CMOS transistors size. However, the performance of nanometre scale CMOSbased designs is limited due to the short-channel effect and process variation. The single electron transistor (SET) is a promising advanced nanometre scale device that can mitigate these grave issues. In this study, a novel SET-based computing system is designed and simulated at a supply voltage of 0.8 V, so that it can be 3D integrated with existing CMOS technology. The SET design parameters are considered based on SET fabricated by nanodamascene process for room temperature operation. The computing system works at frequency of 5 GHz with 2.522 μW power dissipation considering interconnect parasites. The frequency and power dissipation of the SET-based design is nearly 5 times better and 1.6 times lower than for the same design using 16 nm CMOS technology. The results and various analyses show that the SET-based systems are highly efficient and hence very effective to incorporate in next-generation very large scale integration designs. The SET-based design can be also 3D stacked in tandem with existing CMOS technology to achieve higher benefits in terms of speed, power, density, footprint, and functionality.

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Section: Set Design Parameters and Interconnect Parasitic Extractionmentioning

confidence: 99%

“…3, the device's physical parameters for gate capacitance are

W_{g}

t_{g}

, and

d_{g}

whereas for tunnel junction, they are

W_{i}

t_{i}

, and

d_{i}

. The proposed SET has physical parameters

W_{g} = 30 nm

t_{g} = 1 - 10 nm

d_{g} = 20 - 60 nm

W_{i} = 3 - 20 nm

t_{i} = 1 - 10 nm

, and

d_{i} = 2 - 8 nm

, which are considered from [9, 28]. By selecting the appropriate SET physical dimensions it is possible to obtain the desired SET capacitance values.…”

Section: Set‐based Computing System Designmentioning

confidence: 99%

Design of prominent SET‐based high performance computing system

Patel

Agrawal

Parekh

2020

IET Circuits, Devices & Systems

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Section: Introductionmentioning

confidence: 99%

“…SET with a wide operating temperature range up to 130 ˚C can be successfully fabricated with a CMOS compatible back-end-of-line (BEOL) process [6]. SET based low power applications like nonvolatile memory, PLA and logic circuits can be heterogeneously integrated with CMOS circuits [7].Abstract: Heterogeneous 3D integration of single electron transistor (SET) circuits with CMOS based circuits is achieved by stacking a SET layer above CMOS IC. Low power and delay efficient circuits can be designed using SET.…”

mentioning

confidence: 99%

“…A Verilog-A model based on the Mahapatra-Ionescu-Banerjee Model [9] and 16 nm BSIM-CMG high performance predictive model for multi-gate transistors [10,11] is implemented in the spectra circuit simulator and Virtuoso Analog Design Environment of CADENCE [12] for simulation. The SET parameters in this work used for simulation are temperature (T) = 300 K, tunnel resistance (Rt) = 1 MΩ, drain or source capacitance (CD or CS) = 0.03 aF, gate capacitance (CG1) = 0.045 aF and back gate capacitance (CG2) = 0.05 aF [7]. This paper represents an 8 x 8 bit SRAM memory with a memory controller using SET and it can be expanded to n x n bits.…”

mentioning

confidence: 99%

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Design and Simulation of Single Electron Transistor based SRAM and its Memory Controller at Room Temperature

Parekh

2019

IJIE

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IntroductionIntegrated circuits require high speed and low power for processing data. Scaling of technology plays an important role for improvement in the performance of an IC. By technology scaling, the performance of processor can be improved in terms of speed but the speed of a memory is lagging behind the processor speed [1]. Modern SRAM demands high density while maintaining low power consumption and high performance. Presently, the density of SRAM is increasing and it occupies 90 % of the chip area [2]. One of the solutions is to scale the transistor of the SRAM cell. Scaling of the transistor causes velocity saturation, mobility degradation, lower breakdown voltage, increased leakage currents and thus increases in leakage power [3,4]. These challenges of CMOS has motivated numerous novel device like I-MOS, NEMS switch, Spin MOSFET, spin FET, Mott FET and single electron transistor (SET) [5] for either memory or logic applications. SET is a promising and elegant device in nanoelectronics because of its ultra-low power consumption, room temperature operation, scaling potential and CMOS comparable voltage that enables SET to be interfaced with CMOS circuits. SET with a wide operating temperature range up to 130 ˚C can be successfully fabricated with a CMOS compatible back-end-of-line (BEOL) process [6]. SET based low power applications like nonvolatile memory, PLA and logic circuits can be heterogeneously integrated with CMOS circuits [7].Abstract: Heterogeneous 3D integration of single electron transistor (SET) circuits with CMOS based circuits is achieved by stacking a SET layer above CMOS IC. Low power and delay efficient circuits can be designed using SET. In this paper, we have designed and simulated 6T SRAM array operating at room temperature and at CMOS comparable voltage. Peripheral circuit like sense amplifier, decoder, write circuit and pre-charge circuit using SET have been designed for optimum performance. The stability of 6T SRAM cell is verified using N-curve method. The designed SET based 8 x 8 bit SRAM is 99.54 % power efficient, 92.19 % faster in write access time and 78.58 % faster in read access time compared to 16 nm CMOS based SRAM. The SRAM is designed to work at CMOS comparable voltage of 800 mV, which can be scaled up to 20 mV with better efficiency. The designed SRAM is tested and verified for variation in process, voltage and temperature. The maximum frequency of operation for the designed SET based SRAM with memory controller is 4 GHz.

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