Series resistance calculation for source/drain extension regions using 2-D device simulation

Abstract

Series resistance in the source/drain region is becoming a bottleneck for MOS device performance. A rigorous, simulation-based method for calculating resistance components that correctly accounts for current spreading is presented. Resistance calculation strategies used to project lateral abruptness requirements for future scaling, based on partitioning the device into vertical strips, are shown to cause substantial errors when current spreading occurs. This can result in an overestimate of the benefits of abrupt junctions. The physical resistances obtained from simulated devices are compared with the extracted resistances from the shift-and-ratio method. Discrepancies can be explained based on violation of the basic assumptions of the shift-and-ratio method: that series resistance is bias independent and the channel resistance is directly proportional to the channel length. A new extraction method that relaxes these assumptions is presented and used to provide deeper understanding in the application of the shift-and-ratio method to deep submicron devices.

A voltage-dependent channel length extraction method for MOSFET’s

“…It is clear that the short device has a lower R dstr (V g ) than the long and reference ones. This is in agreement with other publications [3] and may result from the charge sharing effects and overlapping region of drain-source resistance which is gate-voltage-dependent [7].…”

“…Kwong et al presented a method [7] in which three devices with different gate-lengths are implemented. In their model they assumed that the drain-source resistance can be ignored in the long channel device in comparison with the channel resistance and minimized the mean-square error between the drain-source resistances of other two devices.…”

Modeling of the Channel Thickness Influence on Electrical Characteristics and Series Resistance in Gate-Recessed Nanoscale SOI MOSFETs

“…where is the series resistance degradation factor (units V −1 ). The decreasing of SD at high positive GS has been already observed in classic MOSFET and LDD device [29,30]. Consequently, can be extracted from for a given SD0 and DS from Figure 4.…”

A Study of Circuit Model Parameter Generation for Giga-Bit Nano Memory Device

“…The transverse mobility is first calibrated with a target of I d −V g which is not relevant to the carrier saturation velocity, and the high field mobility including saturation velocity is then calibrated with a target of I d −V d . 7 The calibration for parameters related with carrier life time, field dependant life time and impact ionization with the target values of BV curve finally makes the accurate simulation for I off and B Vdss possible.…”