Serial interfacing for embedded-memory testing

Nadeau-Dostie, B.; Silburt, A.L.; Agarwal, V.K.

doi:10.1109/54.53045

Cited by 140 publications

(50 citation statements)

References 6 publications

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“…On the other hand, due the limited external access, testing embedded DRAMs is an even more challenging problem than testing monolithic DRAM chips. Here, a number of built-in self-test approaches which have been proposed in the literature can help to develop solutions [1], [2], [4], [5], [6], [7], [8], [10], [14], [15], [16], [18], [19], [21], [23], [28]. A typical BIST architecture is shown in Fig.…”

Section: Introductionmentioning

confidence: 99%

Efficient online and offline testing of embedded DRAMs

Hellebrand

Wunderlich

Ivaniuk

et al. 2002

IEEE Trans. Comput.

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AbstractÐThis paper presents an integrated approach for both built-in online and offline testing of embedded DRAMs. It is based on a new technique for output data compression which offers the same benefits as signature analysis during offline test, but also supports efficient online consistency checking. The initial fault-free memory contents are compressed to a reference characteristic and compared to test characteristics periodically. The reference characteristic depends on the memory contents, but unlike similar characteristics based on signature analysis, it can be easily updated concurrently with WRITE operations. This way, changes in memory do not require a time consuming recomputation. The respective test characteristics can be efficiently computed during the periodic refresh operations of the dynamic RAM. Experiments show that the proposed technique significantly reduces the time between the occurrence of an error and its detection (error detection latency). Compared to error detecting codes (EDC) it also achieves a significantly higher error coverage at lower hardware costs. Therefore, it perfectly complements standard online checking approaches relying on EDC, where the concurrent detection of certain types of errors is guaranteed, but only during READ operations accessing the erroneous data.

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Section: Introductionmentioning

confidence: 99%

Efficient online and offline testing of embedded DRAMs

Hellebrand

Wunderlich

Ivaniuk

et al. 2002

IEEE Trans. Comput.

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“…It also reduces the test time [2]. The research in memory BIST has a long history (see, e.g., [2][3][4][5][6][7][8]). However, most of the BIST approaches proposed so far assume that the BIST circuit is to be integrated with the RAM circuit, whether the BIST circuit is processor based or finite-state machine (FSM) based.…”

Section: Introductionmentioning

confidence: 99%

Processor-programmable memory BIST for bus-connected embedded memories

Tsai

2001

Proceedings of the 2001 Conference on Asia South Pacific Design Automation - ASP-DAC '01

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Abstract-We present a processor-programmable built-in selftest (BIST) scheme suitable for embedded memory testing in the system-on-a-chip (SOC) environment. The proposed BIST circuit can be programmed via an on-chip microprocessor. Upon receiving the commands from the microprocessor, the BIST circuit generates pre-defined test patterns and compares the memory outputs with the expected outputs. Most popular memory test algorithms can be realized by properly programming the BIST circuit using the processor instructions. Compared with processor-based memory BIST schemes that use an assembly-language program to generate test patterns and compare the memory outputs, the test time of the proposed memory BIST scheme is greatly reduced.

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“…In [2], an ad hoc test with no specific fault model was described. In [3], a built-in-self-test (BIST) circuit, based on a serial interfacing technique for embedded two-port (2P) memories, was reported. However, the used fault models were very simplistic, and the proposed BIST requires a modification of the design.…”

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confidence: 99%

Thorough testing of any multiport memory with linear tests

Hamdioui

Goor²

2002

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

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Abstract-The quality of tests, in terms of fault coverage and test length, is strongly dependent on the used fault models. This paper presents realistic fault models for multiport memories with p ports, based on defect injection and SPICE simulation. The results show that the fault models for -port memories consist of p classes: single-port faults, two-port faults,…, -port faults. In addition, the paper discusses the test procedure for such memories; it shows that the time complexity of the required tests is not exponential proportionally with , as published by different authors, but it is linear, irrespective of the number of ports of which the multiport memory consists.

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Serial interfacing for embedded-memory testing

Cited by 140 publications

References 6 publications

Efficient online and offline testing of embedded DRAMs

Efficient online and offline testing of embedded DRAMs

Processor-programmable memory BIST for bus-connected embedded memories

Thorough testing of any multiport memory with linear tests

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