Serial communication protocol for FPGA-based systems

Ivanov, V. K.; Nosov, E. V.

doi:10.1088/1742-6596/1326/1/012044

Cited by 3 publications

(2 citation statements)

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“…Inaccurate baud clocks. Next, we describe a method proposed by Amrit Singh, Khushboo Gupta, and Juhee Mala that describes the determination of an acceptable difference between the transmitter and receiver baud rates for errorfree communication via UART [13].…”

Section: Determination Of Uart Receiver Baudmentioning

confidence: 99%

UART communication protocol frame format explanation and application

Gong,

Guo,

Sun

2023

ACE

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Universal Asynchronous Transceiver (UART) is a Universal Serial Data Bus, hardware communication protocol using asynchronous serial communication in a configurable manner rate. In most embedded systems, microcontrollers and computers, UART plays an important communication role as a hardware communication protocol between devices to ensure the efficient transmission of communication data. The understanding and use of the UART protocol is crucial in our design process. In order to better understand. basic principle this protocol and realize the use of URAT, this paper introduces serial communication, UART frame format explanation, the working principle of UART, simulation of simple UART3. Depending on the source clock, also known as the Baud Clock, each heterogeneous device in a complete system may be able to create a distinct baud rate and connect with other devices over a UART interface. The fundamental tenet of the UART protocol stipulates that for proper communication, the transmitter and receiver must be set at the same baud rate. It also introduces several advanced designs and applications of UART with baud rate, namely UART with automatic frequency generator and frequency divider and Determination of UART Receiver Baud Rate Tolerance.

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Section: Determination Of Uart Receiver Baudmentioning

confidence: 99%

UART communication protocol frame format explanation and application

Gong,

Guo,

Sun

2023

ACE

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“…2) FPGAs Types: Some companies generate different FPGA families but typically follow the standard, scalable, regular, and programmable logic block (CLB) architecture covered by a programmable input/output block perimeter (IOBs). However, in future configuration and architecture, different FPGAs could have a slight variation [40]. Virtex Xilinx is one of the most renowned companies that primarily produces two FPGA family groups: Virtex and Spartan.…”

Section: A Programming Technologiesmentioning

confidence: 99%

FPGA Implementations for Data Encryption and Decryption via Concurrent and Parallel Computation: A Review

Yazdeen

Zeebaree

Sadeeq

et al. 2021

QAJ

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In recent days, increasing numbers of Internet and wireless network users have helped accelerate the need for encryption mechanisms and devices to protect user data sharing across an unsecured network. Data security, integrity, and verification may be used due to these features. In internet traffic encryption, symmetrical block chips play an essential role. Data Encryption Standard (DES) and Advanced Encryption Standard (AES) ensure privacy encryption underlying data protection standards. The DES and the AES provide information security. DES and AES have the distinction of being introduced in both hardware and applications. DES and AES hardware implementation has many advantages, such as increased performance and improved safety. This paper provides an exhaustive study of the implementation by DES and AES of field programming gate arrays (FPGAs) using both DES and AES. Since FPGAs can be defined as just one mission, computers are superior to them.

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