Sequential stress combinations in product level reliability testing of industrial electronics

Pippola, J.; Marttila, Tuomas; Frisk, Laura

doi:10.1109/eptc.2014.7028377

Cited by 1 publication

(1 citation statement)

References 9 publications

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“…[1][2][3][4][5] Besides, it should be noted that products are usually operated under a complicated environment, where the lifetime of products is affected by the combination of multiple stresses. [6][7][8][9] Consequently, to better simulate the failure mechanism in a real use condition, MALT is carried out in a laboratory environment, which can not only make the failure information reflect the performance of products more accurately but also effectively improve the test efficiency for products with high reliability.…”

Section: Introductionmentioning

confidence: 99%

Planning constant‐stress accelerated life tests with multiple stresses based on D‐optimal design

Xiangxiang

Yang

Kong

2020

Quality & Reliability Eng

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With the rapid technological advances, products are becoming more reliable. Then, multistress accelerated life testing (MALT) has been adopted in engineering to obtain failure information in a limited time. In order to make the testing procedure more efficient, it is necessary to better design the test plan. However, to date, relevant research on planning of MALT is limited. Multiple stresses will lead to plenty of stress‐level combinations that require too much cost and time to implement. Besides, there may be interactions among multiple stresses, which need more experiments for parameter estimation. To solve these problems, we propose a novel planning method for constant‐stress MALT under lognormal distribution using D‐optimal design, which can reduce required test points efficiently and deal with second‐order effects in models. In ALT, the log‐linear model is often used to describe the life‐stress relationship. Hence, D‐optimal design is adopted in this paper to select test points from the whole test region. Then, optimal unit allocation plans are formulated under V/D‐optimality criterion, respectively, where type I and type II censoring are both discussed. A real case of light‐emitting device (LED) is presented to compare the proposed approach with other two existing methods. The results show that the proposed method performs better than other two existing methods both in prediction accuracy and estimation precision. Moreover, a sensitivity analysis reveals the robustness of the optimal plans determined by the proposed method.

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