Sequential circuit delay optimization using global path delays

Chakradhar, Srimat; Dey, Sujit; Potkonjak, Miodrag; Rothweiler, S.G.

doi:10.1145/157485.164991

Cited by 16 publications

(5 citation statements)

References 6 publications

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“…In this approach the restructuring and retiming are separate steps, and the method operates on a structural representation of the circuit. Chakradhar et al [1993] presented a technique to optimize the delay of a sequential circuit beyond what is possible with optimal retiming. A set of special timing constraints are derived from the circuit structure and used to resynthesize the combinational component of the circuit.…”

Section: Introductionmentioning

confidence: 99%

Retiming-based factorization for sequential logic optimization

Bommu

O'Neill²,

Ciesielski

2000

ACM Trans. Des. Autom. Electron. Syst.

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Current sequential optimization techniques apply a variety of logic transformations that mainly target the combinational logic component of the circuit. Retiming is typically applied as a postprocessing step to the gate-level implementation obtained after technology mapping. This paper introduces a new sequential logic transformation which integrates retiming with logic transformations at the technology-independent level. This transformation is based on implicit retiming across logic blocks and fanout stems during logic optimization. Its application to sequential network synthesis results in the optimization of logic across register boundaries. It can be used in conjunction with any measure of circuit quality for which a fast and reliable gain estimation method can be obtained. We implemented our new technique within the SIS framework and demonstrated its effectiveness in terms of cycle-time minimization on a set of sequential benchmark circuits.

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Section: Introductionmentioning

confidence: 99%

Retiming-based factorization for sequential logic optimization

Bommu

O'Neill²,

Ciesielski

2000

ACM Trans. Des. Autom. Electron. Syst.

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show abstract

“…Dey et al [3] proposed a method to improve effectiveness of retiming by attempting to eliminate retiming bottlenecks. Chakradhar et al [1] introduced special timing constraints which are used to resynthesize the circuit. The modified circuit is subsequently retimed, and the constraints (if satisfied by the delay optimizer) guarantee that the circuit is retimable and meets the desired cycle time.…”

mentioning

confidence: 99%

Sequential Logic Optimization with Implicit Retiming and Resynthesis

Bommu¹,

Ciesielski²,

O'Neill³

et al. 1997

VLSI: Integrated Systems on Silicon

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This paper* introduces a new logic transformation that integrates retiming with algebraic and Boolean transformations at the technology-independent level. It offers an additional degree of freedom in sequential network optimization resulting from implicit retiming across logic blocks and fanout stems. The application of this transformation to sequential network synthesis results in the optimization of logic across register boundaries. We have implemented our new technique within the SIS framework and demonstrated its effectiveness in terms of cycle-time minimization on a set of sequential benchmark circuits.

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“…Example QC is a queue controller circuit. Example SEQ is a small two-stage sequential circuit that cannot be further optimized by current sequential optimization techniques [9,4,3]. The original cycle in examples FA2 and FA3 is a singlecycle circuit that performs a fetch from a RAM and add operation each cycle.…”

Section: Methodsmentioning

confidence: 99%

“…Peripheral retiming [9] moved registers from the interior of a circuit to its environment to allow the whole circuit to be optimized using combinational optimization. Chakardhar et al took a more timing-driven approach to sequential optimization that results in applying combinational optimization techniques to each stage in the circuit [3]. This technique identies the least stringent set of arrival and required timing constraints which are passed to a combinational delay optimizer along with the circuit.…”

Section: Methodsmentioning

confidence: 99%

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Architectural retiming: pipelining latency-constrained circuits

Hassoun¹,

Ebeling²

33rd Design Automation Conference Proceedings, 1996

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This paper presents a new optimization technique called architectural retiming which is able to improve the performance of many latency-constrained circuits. Architectural retiming achieves this by increasing the number of registers on the latency-constrained path while preserving the functionality and latency of the circuit. This is done using the concept of a negative register, which can be implemented using precomputation and prediction. We use the name architectural retiming since it both reschedules operations in time and modies the structure of the circuit to preserve its functionality. We illustrate the use of architectural retiming on two realistic examples and present performance improvement results for a number of sample circuits.

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Sequential circuit delay optimization using global path delays

Abstract: ABSTRACT:We propose a novel sequential delay op-

Cited by 16 publications

References 6 publications

Retiming-based factorization for sequential logic optimization

Retiming-based factorization for sequential logic optimization

Sequential Logic Optimization with Implicit Retiming and Resynthesis

Architectural retiming: pipelining latency-constrained circuits

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