Sensor/RF digitization for IoT-applications using all-digital-very-scalable-ADC TAD

Watanabe, Toshio; Ishihara, Hideaki; Ito, Tairo

doi:10.23919/mixdes.2017.8004590

Cited by 5 publications

(1 citation statement)

References 29 publications

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“…7 This method is more power and area efficient than other methods using additional element. The literature [7][8][9][10] proposed all-digital time-based ADCs by varying the supply voltage of PMOS transistors in CMOS inverters. As delay cells are the main blocks of time-based ADCs, choosing the right delay cell affects the overall performance of the ADC considerably.…”

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confidence: 99%

An efficient voltage to delay conversion method for DCVSL cells and its application in high speed all‐digital time‐based quantization

Valiollahi

Ardeshir

2019

Circuit Theory & Apps

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Summary Translating the analog input voltage to delay of delay cells is a necessity for realizing digital time‐based quantization. Usually, this conversion is done through additional elements, imposing extra power and area. This paper proposes a voltage to delay conversion method for cross‐coupled differential cascode voltage switch logic (DCVSL) cells, without adding any extra elements to their basic structures. Cross‐coupled delay cells are superior to conventional CMOS inverters in terms of lower power consumption, propagation delay, and area. However, controlling their delay is a demanding task due to their asynchronous charging and discharging. The key features of the proposed method are (a) controlling the delay of DCVSL cells just by see‐saw changing of PMOS transistors source voltages; (b) reducing the propagation delays of DCVSL cells by simultaneously accelerating the charging and discharging processes; (c) reducing the power consumption by decreasing both the switching time and short‐circuit current; (d) employing the proposed voltage to delay conversion method to develop a low power, small area, all‐digital time‐based analog to digital converter (ADC). The proposed 4‐bit ADC, implemented in TSMC 65‐nm CMOS technology, consumes 0.37 mW at conversion speed of 2 GHz with SNDR 20.9 dB and SFDR 30.2 dB, and occupies an active area of 0.0029 mm2.

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confidence: 99%

An efficient voltage to delay conversion method for DCVSL cells and its application in high speed all‐digital time‐based quantization

Valiollahi

Ardeshir

2019

Circuit Theory & Apps

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All-Digital VCO-ADC TAD Using 4CKES-Type in 16-nm FinFET CMOS for Technology Scaling With Stochastic-ADC Method

Watanabe

2021

2021 28th IEEE International Conference on Electronics, Circuits, and Systems (ICECS)

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All-Digital VCO-ADC TAD Confirming Scaling and Stochastic Effects Using 16-nm FinFET CMOS

Watanabe

2021

2021 28th IEEE International Conference on Electronics, Circuits, and Systems (ICECS)

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Sensor/RF digitization for IoT-applications using all-digital-very-scalable-ADC TAD

Cited by 5 publications

References 29 publications

An efficient voltage to delay conversion method for DCVSL cells and its application in high speed all‐digital time‐based quantization

An efficient voltage to delay conversion method for DCVSL cells and its application in high speed all‐digital time‐based quantization

All-Digital VCO-ADC TAD Using 4CKES-Type in 16-nm FinFET CMOS for Technology Scaling With Stochastic-ADC Method

All-Digital VCO-ADC TAD Confirming Scaling and Stochastic Effects Using 16-nm FinFET CMOS

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