Sensitivity-Based Error Resilient Techniques With Heterogeneous Multiply–Accumulate Unit for Voltage Scalable Deep Neural Network Accelerators

Shin, Dongyeob; Choi, Wonseok; Ghosh, Swaroop

doi:10.1109/jetcas.2019.2933862

Cited by 20 publications

(20 citation statements)

References 15 publications

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“…Several studies have particularly considered the design of the MAC units for CNN acceleration [9]- [14]; however, TEC functions were not considered. A convenient method is the direct use of conventional TEC-enabled FWBMs [21]- [32] to devise MAC units for CNNs.…”

Section: Proposed Dual-mode Tec Schemementioning

confidence: 99%

“…The proposed TEC scheme (Mode 1) truncates the N TPminor terms in (13) and uses their estimated value (expressed in (12)) as a substitute. In (13), the original (Eacc+L)-bit MAC result in (8) can be revised as (14), where a global bias (i.e., BM1) is introduced in the TEC operation using (12). In practice, the BM1 value in (14) requires only fractional precision for the w digit using (15), in which a Fw{.}…”

Section: ) Derivation For Mode 1 Tec Schemementioning

confidence: 99%

“…In (13), the original (Eacc+L)-bit MAC result in (8) can be revised as (14), where a global bias (i.e., BM1) is introduced in the TEC operation using (12). In practice, the BM1 value in (14) requires only fractional precision for the w digit using (15), in which a Fw{.} floor function is employed for truncating BM1 to X integer part and w-bit fractional part.…”

Section: ) Derivation For Mode 1 Tec Schemementioning

confidence: 99%

“…Compared with (7) and (8), which are based on conventional TEC-enabled FWBM, BM1 in 14is a global bias accumulating the TEC effect in (12) for each FWBM, thus improving the MAC accuracy by considering overall operations [39]. Moreover, TPmajor of all N FWBMs is accumulated in (14); therefore, the rounding noise only existed in the final stage. Although BM1 in (14) can provide effective global biasing, the calculation for BM1 practically consumes HW costs.…”

Section: ) Derivation For Mode 1 Tec Schemementioning

confidence: 99%

“…Two-dimensional (2D) convolution and inner product computations are the main operations of the convolution and fully connected layers in a CNN [1] and are performed using a series of multiply-accumulate (MAC) operations. Consequently, MAC units are essential components to construct the processing elements (PEs) for CNN acceleration [9]- [14]. By considering the fixed-point MAC operation, a suitable bit width can be determined based on the CNN classification accuracy [8], [15].…”

Section: Introductionmentioning

confidence: 99%

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A High-Accuracy Hardware-Efficient Multiply–Accumulate (MAC) Unit Based on Dual-Mode Truncation Error Compensation for CNNs

Tang

Han

2020

IEEE Access

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This paper presents a multiply-accumulate (MAC) unit that enables a dual-mode truncation error compensation (TEC) scheme based on a fixed-width Booth multiplier (FWBM) for convolutional neural network (CNN) inference operations. The proposed tailored TEC schemes of Modes 1 and 2 can achieve high MAC accuracy for a general or rectified linear unit-based CNN model with general (Mode 1) or positive/zero (Mode 2) input patterns. By pre-calculating the pre-known CNN model coefficients, the proposed dual-mode TEC scheme can be realized using minimal partial product operations with high hardware efficiency using a software-hardware codesign approach. Further, a reconfigurable architecture of the resultant MAC unit is presented to realize the proposed dual-mode TEC scheme. By evaluating the accuracy for 9-N and 25-N MAC operations (N denotes the number of times MAC is performed), a MAC operation using the proposed TEC scheme can achieve the highest accuracy for Modes 1 and 2, relative to contrast samples that directly employ the FWBM with a conventional TEC function. The hardware performances of 9-N and 25-N MAC units are also evaluated using the TSMC 40-nm standard cell library. Compared with the contrast TEC-enabled designs, the proposed MAC unit exhibits higher hardware efficiency in terms of area, delay, and power consumption and achieves a minimum reduction of more than 40% in both area-delay-error and power-delay-error products. Moreover, the resultant 9-N and 25-N MAC units are verified using a system-on-chip field-programmable gate array platform to test a CNN model for handwritten digit classification.

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Section: Proposed Dual-mode Tec Schemementioning

confidence: 99%

Section: ) Derivation For Mode 1 Tec Schemementioning

confidence: 99%

Section: ) Derivation For Mode 1 Tec Schemementioning

confidence: 99%

Section: ) Derivation For Mode 1 Tec Schemementioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

See 3 more Smart Citations

A High-Accuracy Hardware-Efficient Multiply–Accumulate (MAC) Unit Based on Dual-Mode Truncation Error Compensation for CNNs

Tang

Han

2020

IEEE Access

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An Efficient and Reliable Negative Margin Timing Error Detection for Neural Network Accelerator without Accuracy Loss in 28nm CMOS

Shan

et al. 2021

2021 IEEE Asian Solid-State Circuits Conference (A-Sscc)

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Modern Trends in Improving the Technical Characteristics of Devices and Systems for Digital Image Processing

Nagornov,

Lyakhov,

Bergerman

et al. 2024

IEEE Access

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The technology development greatly increases the amount of digital visual information. Existing devices cannot efficiently process such huge amounts of data. The technical characteristics of digital image processing (DIP) devices and systems are being actively improved to resolve this contradiction in science and technology. The state-of-the-art methodology includes a huge number of very diverse approaches at the mathematical, software, and hardware implementation levels. We have analyzed all modern trends to improve the technical characteristics of DIP devices and systems. The main distinguishing feature of this review is that we are not limited to considering various aspects of neural network image processing, to which the vast majority of both review and research papers on the designated topic are devoted. Review papers on the subject under consideration are analyzed. Various mathematical and arithmetic-logical methods for improving the characteristics of image processing devices are described in detail. Original and significant architectural and structural solutions are analyzed. Promising neural network models of visual data processing are characterized. Hardware platforms for the design and operation of DIP systems that are efficient in terms of resource costs are considered. The most significant improvements achieved through the hardware implementation of models and methods on field-programmable gate arrays and application-specific integrated circuits are noted.INDEX TERMS High-performance computing, low-area design, low-power device, energy-efficient architecture, neural network, hardware accelerator, FPGA, ASIC.

show abstract

Sensitivity-Based Error Resilient Techniques With Heterogeneous Multiply–Accumulate Unit for Voltage Scalable Deep Neural Network Accelerators

Cited by 20 publications

References 15 publications

A High-Accuracy Hardware-Efficient Multiply–Accumulate (MAC) Unit Based on Dual-Mode Truncation Error Compensation for CNNs

A High-Accuracy Hardware-Efficient Multiply–Accumulate (MAC) Unit Based on Dual-Mode Truncation Error Compensation for CNNs

An Efficient and Reliable Negative Margin Timing Error Detection for Neural Network Accelerator without Accuracy Loss in 28nm CMOS

Modern Trends in Improving the Technical Characteristics of Devices and Systems for Digital Image Processing

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