Sensitivity based Error Resilient Techniques for Energy Efficient Deep Neural Network Accelerators

Choi, Wonseok; Shin, Dongyeob; Park, Jong Sun; Ghosh, Swaroop

doi:10.1145/3316781.3317908

Cited by 36 publications

(13 citation statements)

References 6 publications

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“…The MAC encountering timing error steals a clock cycle from the downstream MAC to recompute the correct output and bypasses the downstream MAC's output with its output. Choi et al [64] demonstrate a methodology to enhance the resilience of the DNN accelerator based on the sensitivity variations of neurons. The technique detects an error in the multiplier unit by augmenting each MAC unit with a Razor Flip-Flop [36] between multiplier and accumulator unit.…”

Section: Enhancements Around Architecturementioning

confidence: 99%

Challenges and Opportunities in Near-Threshold DNN Accelerators around Timing Errors

Pandey

Gundi

Basu

et al. 2020

JLPEA

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AI evolution is accelerating and Deep Neural Network (DNN) inference accelerators are at the forefront of ad hoc architectures that are evolving to support the immense throughput required for AI computation. However, much more energy efficient design paradigms are inevitable to realize the complete potential of AI evolution and curtail energy consumption. The Near-Threshold Computing (NTC) design paradigm can serve as the best candidate for providing the required energy efficiency. However, NTC operation is plagued with ample performance and reliability concerns arising from the timing errors. In this paper, we dive deep into DNN architecture to uncover some unique challenges and opportunities for operation in the NTC paradigm. By performing rigorous simulations in TPU systolic array, we reveal the severity of timing errors and its impact on inference accuracy at NTC. We analyze various attributes—such as data–delay relationship, delay disparity within arithmetic units, utilization pattern, hardware homogeneity, workload characteristics—and uncover unique localized and global techniques to deal with the timing errors in NTC.

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Section: Enhancements Around Architecturementioning

confidence: 99%

Challenges and Opportunities in Near-Threshold DNN Accelerators around Timing Errors

Pandey

Gundi

Basu

et al. 2020

JLPEA

View full text Add to dashboard Cite

show abstract

“…Previous work [26,33] incorporates circuit-level error detection techniques with architectural error bypassing/masking to mitigate the effect of timing and SRAM errors in voltage underscaled DNN accelerators. The irregular resilience behavior of DNN weights and activations is noted in [3,27], and the described characteristic is utilized to improve the resilience of neural network processing systems through reliability-aware resource allocation techniques. An error-correcting output coding scheme is utilized in [19] to enhance the self-correcting capability of neural networks.…”

Section: Related Workmentioning

confidence: 99%

“…An impacted weight value in a neuron or convolutional filter propagates into the entire channel of activations. 3 If the threshold activations are chosen from the adjacent channels, even the entire channel of anomalous activations in the output feature map could be easily filtered; thus, the weight error resilience of the network could be boosted in both fully connected and convolutional layers.…”

Section: Complementing Variable Suppression Withmentioning

confidence: 99%

“…While DNNs are known to exhibit a noticeable immunity against imprecision and small numerical perturbations, the numerical influence of bit-errors could manifest in quite dramatic terms in digital systems due to the asymmetric weight of the bits in the number representations. The consequent degradation in the accuracy of DNN processing systems has been established in the literature on the topic [3,4,17,21,[25][26][27]33]; additional reliability measures are called for therefore, particularly for critical applications.…”

Section: Introductionmentioning

confidence: 99%

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Just say zero

Ozen

Orailoğlu

2020

Proceedings of the 39th International Conference on Computer-Aided Design

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“…(E-mail: jy1989@mail.tsinghua.edu.cn). popular targets for voltage scaling seeking energy savings [30], [4], [10]. While effective, voltage scaling has the disadvantage of changing circuit delay, which causes timing errors that can lead to degradation of application quality.…”

Section: Introductionmentioning

confidence: 99%

LEVAX: An Input-Aware Learning-Based Error Model of Voltage-Scaled Functional Units

Jiao

Chang

et al. 2020

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

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As Moore's Law comes to an end and transistor scaling increasingly falls short in improving energy efficiency, alternative computing paradigms are direly needed. This need is further highlighted by the overwhelming increase in computing demand posed by emerging applications such as multimedia and data analysis. Fortunately, such driving workloads also present new opportunities since, thanks to their inherent error tolerance, they do not require completely accurate computations. Thus, by trading off accuracy for better performance or improved efficiency, approximate computing promises tremendous growth for future computing. Various approximation methods demonstrate the effectiveness of voltage scaling in functional units (FUs) for exploring this energy-error trade-off. Yet, while an accurate error model is critical for assessing the error behavior of voltagescaled FUs and its effects on application quality, existing error models of voltage-scaled FUs overlook the effects of input data and error rate disparity among different bits. To tackle this challenge, we propose LEVAX, an input-aware learning-based error model of voltage-scaled FUs that can predict the timing error rate (TER) for each output bit. This model is trained using random forest methods, with input features and output labels extracted from gate-level simulations. To validate its effectiveness and demonstrate its prediction accuracy, we use LEVAX on various FUs. Across all bit positions, voltage levels, and FUs, LEVAX achieves, on average, a relative error of 1.20%. LEVAX also achieves an average per-voltage Root Mean Square Error (RMSE) of 1.03% and per-bit RMSE of 1.17%. Exposing this error rate even up to the application level, LEVAX can estimate the quality of four image processing applications under voltage scaling with an average accuracy of 97.9%. To the best of our knowledge, LEVAX is the first voltage scaling error model of FUs that can incorporate the effects of input data.

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Sensitivity based Error Resilient Techniques for Energy Efficient Deep Neural Network Accelerators

Cited by 36 publications

References 6 publications

Challenges and Opportunities in Near-Threshold DNN Accelerators around Timing Errors

Challenges and Opportunities in Near-Threshold DNN Accelerators around Timing Errors

Just say zero

LEVAX: An Input-Aware Learning-Based Error Model of Voltage-Scaled Functional Units

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