Semiconductor process and structural optimization of shallow trench isolation-defined and polysilicon-bound source/drain diodes for ESD networks

Diode-Triggered Silicon-Controlled Rectifier With Reduced Voltage Overshoot for CDM ESD Protection

“…6 suggest that the leakage current of a Poly-DTSCR can likely be reduced below the value shown in Table II simply by changing the gate connection from the anode to the cathode (p + to n + ). Measurement results indicate that such a change also reduces the capacitance of the diode and does not affect its ESD performance, results confirmed by the data in [23] and [24].…”

Silicon on Insulator (SOI) ESD Design

“…SOI lateral diodes for ESD protection can be constructed using a hybrid device that utilizes both the p-channel MOSFET and n-channel MOSFET without the use of body contact structure [10,11,[13][14][15][16]. Using the p-and n-channel source/drain implants, a mask can be placed on the MOSFET gate structure where the p-channel MOSFET source/drain implant forms the anode, and the n-channel MOSFET source/drain forms the cathode.…”

“…Many of the bulk ESD design practices are similar, but new issues need to be addressed in SOI ESD design. In SOI ESD analysis, active areas include SOI electro-thermal simulation and modeling [5-9], experimental work and design integration [11][12][13][14][15][16][17][23][24]27], and SOI patents [10,18,19,21,22,25,[26][27][28][29][30][31][32][33][34][35][36][37][38][39][40].Although many of the basic concepts of ESD design in SOI and bulk CMOS technology are similar, the actual physical layout of the structures and ESD network integration can be significantly different. This has led to the need for new semiconductor devices, new ESD design layout, and new circuit innovations.…”

ESD protection circuits with novel MOS-bounded diode structures

“…To overcome the weakest ESD-damaged lactation at the p/n junction diffusion to the field-oxide boundary, a modified diode structure with dummy gate [7], called as the poly-bounded N-type (P-type) diode, is shown in Figs. 4(a) and 4(b).…”

“…When the diodes are stressed by the ESD pulse under the reverse-biased stress conditions, which are the positive-to-VSS (PS-mode) ESD stress for N-type diode and the negative-to-VDD (ND-mode) ESD stress for P-type diode, the diffusion boundary to the field-oxide isolation is easily damaged by ESD to cause a very low ESD robustness [7]. The weakest point at the boundary between the field-oxide shallow-trench isolation (STI) and the diffusion edge of the diode structure is illustrated in Fig.…”