Semi-Empirical Method for Estimation of Single-Event Upset Cross Section for SRAM DICE Cells

Strategy to mitigate single event upset in 14-nm CMOS bulk FinFET technology

“…13. [8] The presence of guard rings limits the narrowing of NMOS and PMOS spacing. However, with the feature size scaling down and low power required in mobile applications, the supply voltage of the core circuit is usually below 1 V, which means that the latchup problem will not occur in the core circuits.…”

“…[34] In addition to preventing the SEL, the guard rings, which act as taps, also inhibit the charge sharing, thus reducing the SEU cross section in DICE. [8] Therefore, for a combination of transistor location adjustment and DICE design, the guard ring cannot simply be removed, although the latchup problem is no longer a concern for the advanced Fin-FET technology.…”

“…[7] Accordingly, dual DICE interleaving design which can increase the distance between the sensitive nodes in DICE was proposed as a feasible solution. [8,9] For a commercial 65-nm CMOS technology, the dual DICE interleaving cells show about 2-3 orders of magnitude lower in SEU cross sections than the 6T-SRAM cells due to the 2-µm nodal spacing of sensitive pairs, [5] for which the charge sharing between devices is significantly reduced. [10] However, taking 22-nm SOI FinFET device for example, the width of an SRAM cell is about 0.2 µm, [11] which means the 0.4-µm nodal spacing even for an interleaving DICE.…”

“…[17] For the NMOS transistor location adjustment technology, at the minimum distance (160 nm) between NMOS transistor and N-well, the average SET pulse width of 65-nm inverter can be reduced to 18.6% for Ge ion irradiation, while the SET map has not been significantly changed compared withthe SET mapof the maximum distance. [15] In particular, solid guard rings or intermittent rings are used in DICE to prevent the single event latchup (SEL) and charge sharing to occur, [8] which also inhibits the bipolar amplification of PMOS, so are they in HDWC.…”

Current Transients in Graphene Electronics under Single‐Particle Irradiation

“…[ 6 ] However, the state‐of‐the‐art understanding of SEEs is limited to the device performance and relies heavily on semiempirical models. [ 7 ] The underlying microscopic processes of lattice and electronic excitation were not considered. Quantitative measures of the SPI effect are thus mainly on the stopping power and linear transfer energy (LET), while temporal changes in device performance such as the operating current cannot be assessed.…”