Semi-damascene Integration of a 2-layer MOL VHV Scaling Booster to Enable 4-track Standard Cells

Vega-Gonzalez, V.; Radisic, Dunja; Choudhury, S.; Tierno, Davide; Thiam, A.; Batuk, D.; Martinez, G.T.; Seidel, F. C.; Decoster, Stefan; Kundu, Shreya; Tsvetanova, Diana; Peter, A.; Coster, H. De; Sepulveda-Marquez, A.; Altamirano-Sánchez, Efraín; Chan, B. T.; Drissi, Youssef; Sherazi, Yasser; Uk-Lee, J.; Ciofi, Ivan; Murdoch, Gayle; Nagesh, N.; Hellings, Geert; Ryckaert, Julien; Biesemans, S.; Litta, Eugenio Dentoni; Horiguchi, N.; Park, S.; Tőkei, Zs.

doi:10.1109/iedm45625.2022.10019483

Cited by 3 publications

(3 citation statements)

References 9 publications

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“…Recently, more advanced BEOL integration schemes such as direct metal etch (DME), self-aligned cuts (SAC), semidamascene integration [32][33][34][35][36][37][38][39][40], and upward self-aligned vias (SAV, connected to upper metal lines [35,41]) processes were reported. However, none of them integrated both upward and downward SAVs into the metallization process flow.…”

Section: Rigorously Self-aligned Vias and Cuts: Direct Ru Dry Etch An...mentioning

confidence: 99%

“…As a promising candidate of barrierless interconnect material, Ru and its direct metal etching for a semi-damascene metallization process have been extensively researched [32][33][34][35][36][37][38][39][40]. There are other metals such as Mo, W, Co that can be etched for a controllable metal recess.…”

Section: Rigorously Self-aligned Vias and Cuts: Direct Ru Dry Etch An...mentioning

confidence: 99%

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Mandrel/spacer engineering-based patterning and metallization incorporating metal layer division and rigorously self-aligned vias and cuts (SAVC)

Chen,

Sun,

Song

et al. 2024

Advanced Etch Technology and Process Integration for Nanopatterning XIII

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In this paper, we first present a brief review of the advanced-node logic device technology development and its key bottleneck/component processes using the existing lithographic capabilities. It is shown to be feasible to evolve into the GAA era with the minimum change of current FinFET process and a minor refining of previously reported Forksheet structure. The concept of hybrid-channel devices is raised which is not only promising for 3D vertical integration, but also offers an optimal tradeoff between device performance and power/leakage. To address the fabrication challenges, a mandrel/spacer engineering based patterning and metallization technology is proposed and its process development results are reported. This patterning & metallization technique can be applied to fabricate advanced logic and SRAM circuits with significantly enhanced pattern density. It is based on the self-aligned multiple patterning (SAMP) wherein either an alternating arrangement of different materials (with high etching selectivity) or multi-color layer decomposition (i.e., splitting of metallization process) is utilized to solve the edge-placement-error (EPE) issue. In particular, we explore various schemes of self-aligned triple patterning (SATP) to identify the potential solution to ensure a satisfactory profile control of the consecutively formed spacers. Moreover, this technique can incorporate rigorously self-aligned vias & cuts (SAVC), and accommodate a metal-layer division (MLD) to split the neighboring metal lines into two vertically staggered layers with their coupling capacitance significantly reduced. The tested metal Ru allows a direct dry etching, which offers a metal recess capability to enable an alternating-material coverage of neighboring metal wires by two different hard masks such that a selective etching can be applied to form rigorously self-aligned vias. Our early-stage process development is focused on SATP process optimization, fabrication of two simplified grating structures, material screening for appropriate etching selectivity, and metal-layerdivision realization. Potential processing challenges such as Ru trench-filling quality and scaling issues of SAVC technology for advanced IC manufacturing will also be discussed.

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Section: Rigorously Self-aligned Vias and Cuts: Direct Ru Dry Etch An...mentioning

confidence: 99%

Section: Rigorously Self-aligned Vias and Cuts: Direct Ru Dry Etch An...mentioning

confidence: 99%

Mandrel/spacer engineering-based patterning and metallization incorporating metal layer division and rigorously self-aligned vias and cuts (SAVC)

Chen,

Sun,

Song

et al. 2024

Advanced Etch Technology and Process Integration for Nanopatterning XIII

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show abstract

“…The only exception (without using CFET) is the VHV architecture, where an additional vertical MOL layer is added to reduce routing congestions, and the effective active width is maintained by the Forksheet architecture. [8,9] However, CFET also allows further scaling down to 3T (Fig. 6a).…”

Section: Cfet Scaling: Logic and Srammentioning

confidence: 99%

Design-technology co-optimization overview of CFET architecture

Mirabelli

Schuddinck

Liu

et al. 2023

DTCO and Computational Patterning II

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Fin depopulation, thinner and taller fins, and the step towards Nanosheet technologies has been helping in maintaining the rhythm of the semiconductor technology roadmap. Nevertheless, further area scaling causes a drastic reduction in active width as well as a challenging routability. On this regard, the Complementary-FET is a strong contender as device for next generation technologies. The stack of p- on n-FETs offers several opportunities for device scaling and optimization. However, it also poses several challenges that need to be carefully analyzed in a design-technology cooptimization framework.

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Insight Into Electromigration Reliability of Buried Power Rail With Alternative Metal Material

Cai,

Chen,

Zhang

et al. 2024

IEEE Trans. Electron Devices

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Semi-damascene Integration of a 2-layer MOL VHV Scaling Booster to Enable 4-track Standard Cells

Cited by 3 publications

References 9 publications

Mandrel/spacer engineering-based patterning and metallization incorporating metal layer division and rigorously self-aligned vias and cuts (SAVC)

Mandrel/spacer engineering-based patterning and metallization incorporating metal layer division and rigorously self-aligned vias and cuts (SAVC)

Design-technology co-optimization overview of CFET architecture

Insight Into Electromigration Reliability of Buried Power Rail With Alternative Metal Material

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